Package substrate and fabricating method thereof

Abstract

There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.

1 . A package substrate, comprising:
 a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region;   a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity;   a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer;   a through-hole penetrating through the wafer and a via filling the through-hole; and   one or more electronic device connected to the via.   
     
     
         2 . The package substrate of  claim 1 , wherein the via is connected to the electronic device or an external device through solder bumps. 
     
     
         3 . The package substrate of  claim 1 , wherein the chip is a multilayer ceramic capacitor (MLCC). 
     
     
         4 . The package substrate of  claim 1 , wherein the electronic device is at least one selected from a resistor and an inductor. 
     
     
         5 . The package substrate of  claim 1 , wherein the wafer is made of silicon. 
     
     
         6 . The package substrate of  claim 1 , further comprising an insulating layer formed to cover the chip and the electronic device and exposing a portion of the first and second wiring layers. 
     
     
         7 . A method of fabricating a package substrate, comprising:
 forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region;   forming a through-hole penetrating through the wafer and a via filling the through-hole;   forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity; and   mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.   
     
     
         8 . The method of  claim 7 , further comprising a polishing at least one of the upper surface and a lower surface of the wafer before the forming of the cavity. 
     
     
         9 . The method of  claim 7 , wherein the forming of the cavity includes:
 forming a first insulating film on the upper surface of the wafer;   forming a first insulating pattern for forming the cavity by etching the first insulating film; and   forming the cavity by etching the wafer using the first insulating pattern.   
     
     
         10 . The method of  claim 9 , wherein the forming of the cavity by etching the wafer includes wet etching of the wafer using a potassium hydroxide (KOH) solution. 
     
     
         11 . The method of  claim 7 , wherein the forming of the through-hole includes:
 forming a first photosensitive resin layer on the upper surface or a lower surface of the wafer;   forming a first photosensitive pattern by exposing and developing the first photosensitive resin layer; and   forming the through-hole by etching the wafer using the first photosensitive pattern.   
     
     
         12 . The method of  claim 7 , wherein the forming of the via includes:
 forming a second insulating film on a surface of the wafer including the through-hole and the cavity;   forming a plating seed layer on the second insulating film; and   filling the through-hole with a conductive material using an electroplating method.   
     
     
         13 . The method of  claim 7 , wherein the forming of the first wiring layer and the second wiring layer includes:
 forming a second photosensitive pattern on a region in the wafer, in which the first wiring layer and the second wiring layer are not formed;   forming a wiring material on the upper surface of the wafer;   removing the second photosensitive pattern and the wiring material formed on the second photosensitive pattern using a lift-off method.   
     
     
         14 . The method of  claim 7 , further comprising bonding the chip to each of the first wiring layer and the second wiring layer by allowing the wafer to reflow, after the mounting of the chip in the cavity. 
     
     
         15 . The method of  claim 7 , wherein the chip is a multilayer ceramic capacitor (MLCC). 
     
     
         16 . The method of  claim 7 , wherein the electronic device is at least one selected from a resistor and an inductor. 
     
     
         17 . The method of  claim 7 , further comprising forming an insulating layer exposing a portion of the first and second wiring layers and covering the chip and the electronic device. 
     
     
         18 . The method of  claim 7 , further comprising connecting the via to the electronic device or an external device through solder bumps.