US2011234304A1PendingUtilityA1

On-Chip Redundancy High-Reliable System and Method of Controlling the Same

Assignee: HITACHI LTDPriority: Feb 19, 2009Filed: Jun 3, 2011Published: Sep 29, 2011
Est. expiryFeb 19, 2029(~2.6 yrs left)· nominal 20-yr term from priority
G06F 11/1645G06F 11/1641G06F 11/165
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Claims

Abstract

The present invention is directed to improve reliably of an on-chip redundancy system by preventing influence of a physical failure exerted on an entire semiconductor chip. A comparator measure for comparing outputs of an on-chip redundancy system is mounted on a semiconductor chip different from the on-chip redundancy system. The another semiconductor chip is, preferably, mounted on a semiconductor chip on which a power source circuit for supplying power to the on-chip redundancy system redundantly having the comparing function in the chip, a driver circuit for driving an output circuit, and the like are mounted. With the configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure.

Claims

exact text as granted — not AI-modified
1 . Anon-chip redundancy highly-reliable system comprising:
 at least two function blocks having the same function and redundantly provided in a first semiconductor chip; and   a comparator measure for comparing outputs of the function blocks and provided in a second semiconductor chip.

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