Integrated circuit including power diode

Abstract

A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

1 - 12 . (canceled) 
     
     
         13 . A method of fabricating an integrated circuit including a power diode in a semiconductor body comprising the steps of:
 a) providing a semiconductor substrate including a surface layer of first conductivity type.   b) forming a dielectric material in a surface of the semiconductor substrate around a first region in which a power diode is to be fabricated and separated from a second region in which an integrated circuit is to be fabricated,   c) forming semiconductor material of a second conductivity type in the first region,   d) fabricating an integrated circuit in the second region,   e) fabricating a plurality of MOS source/drain elements and associated gate elements in a surface of the device region and in the semiconductor material of second conductivity type,   f) forming a first diode electrode contacting the plurality of MOS source/drain elements and associated gate elements,   g) forming a conductive via from the surface of the device region to the semiconductor material of second conductivity type as a second diode electrode.   
     
     
         14 . The method of  claim 13  wherein step b) includes forming a trench in the first region, and forming dielectric side wall spacers on the trench, and step c) includes epitaxially growing semiconductor material of second conductivity type in the trench. 
     
     
         15 . The method of  claim 13  wherein step b) includes forming dielectric material in a surface of the semiconductor substrate, and step c) includes implanting dopant of second conductivity type into the first region. 
     
     
         16 . The method as defined by  claim 13  and further including the step of:
 h) forming a doped guard ring of first conductivity type in the first region abutting the dielectric material. 
 
     
     
         17 . The method as defined by  claim 16  and further including the step of:
 i) forming a plug of first conductivity type in the first region extending into the semiconductor material of second type. 
 
     
     
         18 . The method as defined by  claim 13  wherein step g) includes forming dielectric spacers between the conductive via and the plurality of MOS source/drain elements. 
     
     
         19 . The method as defined by  claim 13  wherein step d) includes forming a plurality of P wells and a plurality of N wells for CMOS transistors.