Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same

Abstract

A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

1 - 12 . (canceled) 
     
     
         13 . A method of manufacturing a semiconductor device, comprising:
 preparing a silicon substrate;   forming an insulator on the silicon substrate;   forming a silicon layer having diffusion layers and a channel region between the diffusion layers on the insulator;   forming a metal layer on the diffusion layers;   forming a first silicide layer in a first stable phase in an area of each diffusion layer by performing a first thermal treatment on the silicon substrate; and   phase-transforming the first silicide layer to a second silicide layer in a second stable phase, and expanding each second silicide layer in another area of one of the diffusion layers by performing on the silicon substrate a second thermal treatment at a temperature higher than a temperature of the first thermal treatment, wherein each second silicide layer reaches the insulator and the diffusion layers adjacent to the channel region remains;   wherein the second thermal treatment forms interface junctions, each including a (111) silicon plane between one of the remaining diffusion layer and one of the second silicide layer.   
     
     
         14 . A method of manufacturing a semiconductor device as claimed in  claim 13 , each second silicide layer includes di-silicide, and a concentration of metal contained in the first silicide is higher than that contained in the second silicide. 
     
     
         15 . A method of manufacturing a semiconductor device as claimed in  claim 13 , the second thermal treatment forms the interface junctions, each further including a (111) metal silicide plane. 
     
     
         16 - 20 . (canceled) 
     
     
         21 . A method of manufacturing a semiconductor device, comprising:
 preparing a silicon substrate;   forming an insulator on the silicon substrate;   forming a silicon layer having diffusion layers and a channel region between the diffusion layers on the insulator;   forming a metal layer on the diffusion layers;   forming a first silicide layer in a first stable phase in an area of each diffusion layer by performing a first thermal treatment on the silicon substrate;   phase-transforming the first silicide layer to a second silicide layer in a second stable phase, and expanding each second silicide layer in another area of one of the diffusion layers by performing a second thermal treatment on the silicon substrate until a bottom of each second silicide layers reaches the insulator; and   phase-transferring the second silicide layer to a third silicide layer in a third stable phase, and expanding each third silicide layer in other areas in one of the diffusion layer toward the channel region by performing a third thermal treatment on the silicon substrate while the diffusion layers adjacent to the channel region remains, wherein temperatures of the second or third thermal treatment are higher than a temperature of the first thermal treatment;   wherein the third thermal treatment forms interface junctions, each including a (111) silicon plane between one of the remaining diffusion layers and one of the second silicide layers.   
     
     
         22 . A method of manufacturing a semiconductor device as claimed in  claim 21 , each third silicide layer includes di-silicide, and a concentration of metal contained in the first or second silicide layer is high than that contained in the third silicide layer. 
     
     
         23 . A method of manufacturing a semiconductor device as claimed in  claim 21 , a concentration of metal contained in the first silicide layer is higher than that contained in the second silicide layer. 
     
     
         24 . A method of manufacturing a semiconductor device as claimed in  claim 21 , the third thermal treatment forms the interface junctions, each further including a (111) metal silicide plane. 
     
     
         25 - 30 . (canceled)