System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process

Abstract

A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.

1 - 16 . (canceled) 
     
     
         17 . An anti-fuse in an integrated circuit comprising:
 a silicon layer that comprises a portion of P type silicon and an adjacent portion of N type silicon;   a dielectric layer over the silicon layer; and   a tungsten plug through the dielectric layer, the tungsten plug is in electrical contact with the portion of P type silicon;   wherein the dielectric layer has a first contact opening through the dielectric layer down to the portion of P type silicon; and   wherein the dielectric layer has a second contact opening through the dielectric layer down to the adjacent portion of N type silicon.   
     
     
         18 . The anti-fuse as claimed in  claim 17 , further comprising:
 a metal layer over the etched dielectric layer, over the tungsten plug, over the portion of P type silicon, and over the adjacent portion of N type silicon.   
     
     
         19 . The anti-fuse as claimed in  claim 18 , wherein:
 the metal layer comprises a first portion that forms a first anti-fuse contact in electrical contact with the portion of P type silicon; and   the metal layer comprises a second portion that forms a second anti-fuse contact in electrical contact with the portion of N type silicon.   
     
     
         20 . The anti-fuse as claimed in  claim 19 , further comprising:
 an electrically conductive path from the first anti-fuse contact through the portion of P type silicon and through the adjacent portion of N type silicon to the second anti-fuse contact.   
     
     
         21 . The anti-fuse as claimed in  claim 20 , wherein the electrically conductive path through the portion of P type silicon and through the portion of N type silicon passes under a LOCOS isolation structure located at a junction between the portion of P type silicon and the portion of N type silicon. 
     
     
         22 . The anti-fuse as claimed in  claim 19 , wherein the metal layer comprises a third portion separate from the first and second portions of the metal layer, the third portion of the metal layer in electrical contact with the tungsten plug. 
     
     
         23 . The anti-fuse as claimed in  claim 19 , wherein:
 the first portion of the metal layer comprises aluminum partially filling the first contact opening; and   the second portion of the metal layer comprises aluminum partially filling the second contact opening.   
     
     
         24 . The anti-fuse as claimed in  claim 19 , wherein the first and second portions of the metal layer are separated by an opening located over a junction between the portion of P type silicon and the portion of N type silicon. 
     
     
         25 . The anti-fuse as claimed in  claim 17 , further comprising:
 a contact salicide at a bottom of the first contact opening.   
     
     
         26 . An anti-fuse in an integrated circuit comprising:
 a silicon layer that comprises a portion of P type silicon and an adjacent portion of N type silicon in physical contact with the portion of P type silicon;   a dielectric layer over the silicon layer, wherein the dielectric layer has a first contact opening through the dielectric layer to the portion of P type silicon, and wherein the dielectric layer has a second contact opening through the dielectric layer to the portion of N type silicon;   a conductive plug through the dielectric layer, wherein the conductive plug is in electrical contact with the portion of P type silicon; and   a conductive layer comprising (i) a first portion that forms a first anti-fuse contact through the first contact opening in electrical contact with the portion of P type silicon and (ii) a second portion that form a second anti-fuse contact through the second contact opening in electrical contact with the portion of N type silicon.   
     
     
         27 . The anti-fuse as claimed in  claim 26 , further comprising:
 an electrically conductive path from the first anti-fuse contact through the portion of P type silicon and through the portion of N type silicon to the second anti-fuse contact.   
     
     
         28 . The anti-fuse as claimed in  claim 27 , wherein the electrically conductive path through the portion of P type silicon and through the portion of N type silicon passes under a LOCOS isolation structure located at a junction between the portion of P type silicon and the portion of N type silicon. 
     
     
         29 . The anti-fuse as claimed in  claim 26 , wherein the conductive layer further comprises a third portion separate from the first and second portions of the conductive layer, the third portion of the conductive layer in electrical contact with the conductive plug. 
     
     
         30 . The anti-fuse as claimed in  claim 26 , further comprising:
 a contact salicide at a bottom of the first contact opening.   
     
     
         31 . The anti-fuse as claimed in  claim 26 , wherein:
 the first portion of the conductive layer comprises aluminum partially filling the first contact opening; and   the second portion of the conductive layer comprises aluminum partially filling the second contact opening.   
     
     
         32 . The anti-fuse as claimed in  claim 26 , wherein the first and second portions of the conductive layer are separated by an opening located over a junction between the portion of P type silicon and the portion of N type silicon. 
     
     
         33 . An anti-fuse in an integrated circuit comprising:
 a semiconductor layer comprising a portion of P type semiconductor and an adjacent portion of N type semiconductor in physical contact with the portion of P type semiconductor;   a dielectric layer over the semiconductor layer;   a conductive plug through the dielectric layer, wherein the conductive plug is in electrical contact with the portion of P type semiconductor; and   a conductive layer over the dielectric layer and over the semiconductor layer, the conductive layer comprising (i) a first portion that forms a first anti-fuse contact through a first contact opening of the dielectric layer in electrical contact with the portion of P type semiconductor and (ii) a second portion that forms a second anti-fuse contact through a second contact opening of the dielectric layer in electrical contact with the portion of N type semiconductor.   
     
     
         34 . The anti-fuse as claimed in  claim 33 , wherein the first and second portions of the conductive layer are separated by an opening located over a junction between the portion of P type semiconductor and the portion of N type semiconductor. 
     
     
         35 . The anti-fuse of  claim 33 , further comprising:
 an electrically conductive path from the first anti-fuse contact through the portion of P type semiconductor and through the portion of N type semiconductor to the second anti-fuse contact.   
     
     
         36 . The anti-fuse as claimed in  claim 35 , wherein the electrically conductive path through the portion of P type semiconductor and through the portion of N type semiconductor passes under a LOCOS isolation structure located at a junction between the portion of P type semiconductor and the portion of N type semiconductor.