US2011215469A1PendingUtilityA1

Method for forming a double embossing structure

47
Assignee: MEGICA CORPPriority: Jul 22, 2005Filed: May 16, 2011Published: Sep 8, 2011
Est. expiryJul 22, 2025(expired)· nominal 20-yr term from priority
Inventors:Hsin-Jung LoMou-Shiung LinChiu-Ming ChouChien-Kang Chou
H10W 72/5522H10W 72/5525H10W 72/536H10W 72/952H10W 72/9415H10W 72/934H10W 72/29H10W 72/59H10W 72/923H10W 72/90H10W 72/01955H10W 72/983H10W 70/05H10W 72/851H10W 72/251H10W 72/252H10W 72/242H10W 72/01255H10W 20/071H10P 14/69433H10P 14/69215H10P 14/662H10P 14/47
47
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Claims

Abstract

A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

Claims

exact text as granted — not AI-modified
1 - 20 . (canceled) 
     
     
         21 . A circuit component comprising:
 a device comprising a glass substrate and a first metal layer under said glass substrate; and   a chip under said device, wherein said chip comprises a silicon substrate, a second metal layer over said silicon substrate, wherein said second metal layer comprises a coil, a dielectric layer over said second metal layer and said silicon substrate, and a metal bump over said silicon substrate, wherein said metal bump contacts said first metal layer.   
     
     
         22 . The circuit component of  claim 21 , wherein said first metal layer comprises gold. 
     
     
         23 . The circuit component of  claim 21 , wherein said first metal layer comprises tin. 
     
     
         24 . The circuit component of  claim 21 , wherein said second metal layer comprises copper. 
     
     
         25 . The circuit component of  claim 21 , wherein said second metal layer comprises a copper layer having a thickness between 1 and 20 micrometers. 
     
     
         26 . The circuit component of  claim 21 , wherein said metal bump comprises a third metal layer on said second metal layer and a fourth metal layer on said third metal layer. 
     
     
         27 . The circuit component of  claim 21 , wherein said metal bump comprises copper. 
     
     
         28 . The circuit component of  claim 21 , wherein said metal bump comprises nickel. 
     
     
         29 . The circuit component of  claim 21 , wherein said metal bump comprises gold. 
     
     
         30 . The circuit component of  claim 21 , wherein said metal bump comprises a copper layer having a thickness between 2 and 30 micrometers. 
     
     
         31 . The circuit component of  claim 21 , wherein said metal bump comprises a third metal layer on said second metal layer and a tin-containing layer on said third metal layer. 
     
     
         32 . The circuit component of  claim 21 , wherein said dielectric layer comprises a polymer. 
     
     
         33 . The circuit component of  claim 21 , wherein said chip comprises a polymer layer over said silicon substrate, wherein said second metal layer is further on said polymer layer. 
     
     
         34 . A chip comprising:
 a silicon substrate;   a first coil over said silicon substrate;   a dielectric layer over said first coil and said silicon substrate; and   a second coil over said dielectric layer, wherein said second coil is vertically over said first coil and connected to said first coil.   
     
     
         35 . The chip of  claim 34 , wherein said first coil comprises copper. 
     
     
         36 . The chip of  claim 34 , wherein said first coil comprises a copper layer having a thickness between 1 and 20 micrometers. 
     
     
         37 . The chip of  claim 34 , wherein said second coil comprises copper. 
     
     
         38 . The chip of  claim 34 , wherein said second coil comprises a copper layer having a thickness between 1 and 20 micrometers. 
     
     
         39 . The chip of  claim 34 , wherein said dielectric layer comprises a polymer. 
     
     
         40 . The chip of  claim 34  further comprising a polymer layer over said silicon substrate, wherein said first coil is further on said polymer layer. 
     
     
         41 . The chip of  claim 34  further comprising a polymer layer over said second coil and said dielectric layer. 
     
     
         42 . The chip of  claim 34 , wherein said first coil is provided by a patterned circuit layer comprising a first metal layer and a second metal layer on said first metal layer, wherein said second metal layer has a sidewall not covered by said first metal layer. 
     
     
         43 . The chip of  claim 42 , wherein said first metal layer comprises titanium. 
     
     
         44 . The chip of  claim 34 , wherein said second coil is provided by a patterned circuit layer comprising a first metal layer and a second metal layer on said first metal layer, wherein said second metal layer has a sidewall not covered by said first metal layer. 
     
     
         45 . The chip of  claim 44 , wherein said first metal layer comprises titanium. 
     
     
         46 . A chip comprising:
 a substrate;   a first dielectric layer over said substrate;   a patterned circuit layer on said first dielectric layer and over said substrate;   a second dielectric layer on said patterned circuit layer and on said first dielectric layer, wherein said patterned circuit layer has a contact point and left and right regions not covered by said second dielectric layer, wherein said contact point is between said left and right regions; and   a metal bump on said contact point, wherein said metal bump comprises a copper layer, wherein said metal bump has a left sidewall horizontally spaced apart from a left portion of said second dielectric layer, and said left region is between said left sidewall and said left portion, wherein said metal bump has a right sidewall horizontally spaced apart from a right portion of said second dielectric layer, and said right region is between said right sidewall and said right portion, wherein said second dielectric layer has no portion between said left sidewall and said left portion and between said right sidewall and said right portion.   
     
     
         47 . The chip of  claim 46 , wherein said copper layer has a height between 2 and 30 micrometers. 
     
     
         48 . The chip of  claim 46 , wherein said patterned circuit layer comprises a first metal layer and a second metal layer on said first metal layer, wherein said second metal layer has a sidewall not covered by said first metal layer. 
     
     
         49 . The chip of  claim 48 , wherein said first metal layer comprises titanium. 
     
     
         50 . The chip of  claim 48 , wherein said first metal layer comprises titanium nitride. 
     
     
         51 . The chip of  claim 48 , wherein said first metal layer comprises tantalum. 
     
     
         52 . The chip of  claim 48 , wherein said first metal layer comprises tantalum nitride. 
     
     
         53 . The chip of  claim 48 , wherein said second metal layer comprises copper. 
     
     
         54 . The chip of  claim 46 , wherein said second dielectric layer comprises a polymer. 
     
     
         55 . The chip of  claim 46 , wherein said first dielectric layer comprises a polymer. 
     
     
         56 . The chip of  claim 46 , wherein said substrate comprises damascene copper.

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