ESD Protection Devices

Abstract

An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

1 . An ESD protection device comprising:
 a first semiconductor controlled rectifier (SCR) coupled between a high voltage source and a ground; and   an ESD detection circuit detecting whether an ESD event occurs;   wherein when the ESD detection circuit detects that the ESD event occurs, the ESD detection circuit provides a first voltage and a second voltage to the first SCR, so that the first SCR provides a first discharging path.   
     
     
         2 . The ESD protection device as claimed in  claim 1  further comprising a second SCR coupled between an I/O pad and the ground, wherein when the ESD detection circuit detects that the ESD event occurs, the ESD detection circuit provides the first voltage and the second voltage to the second SCR, so that the second SCR provides a second discharging path. 
     
     
         3 . The ESD protection device as claimed in  claim 2 , wherein each of the first and second SCRs comprises:
 a first MOS transistor having a gate, a source coupled to a first node, and a drain coupled to a second node;   a first BJT transistor having a base coupled to a third node, an emitter coupled to the first node, and a collector coupled to the second node;   a first resistance coupled between the first and third nodes;   a second MOS transistor having a gate, a drain coupled to the third node, and a source coupled to a fourth node;   a second BJT transistor having a base coupled to the second node, a collector coupled to the third node, and an emitter coupled to the fourth node; and   a second resistor coupled between second and fourth nodes.   
     
     
         4 . The ESD protection device as claimed in  claim 3 , wherein the gates of the first MOS transistors of the first and second SCRs receive the first voltage, and the gates of the second MOS transistors of the first and second SCRs receive the second voltage. 
     
     
         5 . The ESD protection device as claimed in  claim 4 , wherein the first node of the first SCR is coupled to the high voltage source, and the fourth node of the first SCR is coupled to the ground. 
     
     
         6 . The ESD protection device as claimed in  claim 5 , wherein the first node of the second SCR is coupled to the I/O pad, and the fourth node of the second SCR is coupled to the ground.