Phosphorus Activated NMOS Using SiC Process

Abstract

A method ( 10 ) of forming a transistor ( 100 ) includes treating ( 12 ) at least some of a semiconductor substrate ( 102 ) with carbon and then forming ( 18 ) a gate structure ( 114 ) over the semiconductor substrate. A channel region ( 122 ) is thereby being defined within the semiconductor substrate ( 102 ) below the gate structure ( 114 ). Source and drain regions ( 140, 142 ) are then formed ( 26 ) within the semiconductor substrate ( 102 ) on opposing sides of the channel ( 122 ) with a phosphorus dopant.

1 - 14 . (canceled) 
     
     
         15 . A method of forming a transistor, comprising:
 forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate under the gate structure;   etching portions of the substrate on opposing sides of the channel region;   forming silicon carbon material within the etched portions of the substrate; and   forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant.   
     
     
         16 . The method of  claim 15 , wherein the silicon carbon material is epitaxially grown. 
     
     
         17 . The method of  claim 15 , further comprising:
 forming sidewall spacers adjacent to the gate structure prior to etching the substrate, etched portions of the substrate thereby being substantially aligned with the sidewall spacers.   
     
     
         18 . The method of  claim 17 , wherein the silicon carbon material is epitaxially grown. 
     
     
         19 . The method of  claim 15 , further comprising:
 forming offset spacers adjacent to the gate structure prior to etching the substrate, etched portions of the substrate thereby being substantially aligned with the offset spacers.   
     
     
         20 . The method of  claim 19 , wherein the substrate is etched to a depth of between about 200 angstroms to about 400 angstroms. 
     
     
         21 . A method of forming a transistor comprising:
 forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;   etching portions of the substrate on opposing sides of the channel region;   forming silicon carbon material within the etched portions of the substrate;   forming sidewall spacers adjacent to the gate structure;   forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;   etching away the sidewall spacers;   forming offset spacers adjacent to the gate structure; and   forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers.   
     
     
         22 . A method of forming a transistor comprising:
 forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;   forming sidewall spacers adjacent to the gate structure;   forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;   etching the sidewall spacers and portions of the source and drain regions within the substrate;   forming silicon carbon material within etched portions of the substrate;   forming offset spacers adjacent to the gate structure; and   forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers.   
     
     
         23 . A method of forming a transistor comprising:
 forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;   forming sidewall spacers adjacent to the gate structure;   forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;   etching away the sidewall spacers;   forming offset spacers adjacent to the gate structure;   forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers;   etching the portions of the source and drain regions and extension regions within the substrate; and   forming silicon carbon material within etched portions of the substrate.