Semiconductor storage device

Abstract

A voltage of a bit line connected to a memory cell is stepped up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply.

1 - 4 . (canceled) 
     
     
         5 . A semiconductor storage device comprising:
 a memory cell,   a first bit line connected to the memory cell,   a precharge circuit for stepping up a voltage of the first bit line, and   a power supply connecting circuit for supplying a high-potential-side power to the precharge circuit,   a ground connecting circuit for supplying a low-potential-side power to the precharge circuit,   wherein the pre charge circuit steps up a voltage of the bit line by supplying the high-potential-side power to the first bit line,   the precharge circuit steps down a voltage of the bit line by supplying the low-potential-side power to the first bit line, and   the precharge circuit comprises a first PMOS transistor of which source is supplied one of the high-potential-side power from the power supply connecting circuit and the low-potential-side power from the ground connecting circuit, and of which drain supplies one of the high-potential-side power and the low-potential-side power to the first bit line.   
     
     
         6 . The semiconductor storage device as claimed in  claim 5 , further comprises:
 a second bit line connected to the memory cell,   wherein the pre charge circuit further comprises a second PMOS transistor of which source is supplied one of the high-potential-side power from the power supply connecting circuit and the low-potential-side power from the ground connecting circuit, and of which drain supplies one of the high-potential-side power and the low-potential-aide power to the second bit line.   
     
     
         7 . The semiconductor storage device as claimed in  claim 6 , wherein the memory cell is an SRAM. 
     
     
         8 . The semiconductor storage device as claimed in  claim 6 , wherein
 the power supply connecting circuit comprises a third transistor of which source is supplied the high-potential-side power from a high potential-side power supply and drain supplies the high-potential-side power to the precharge circuit, and   the ground connecting circuit comprises a fourth transistor of which source is supplied the low-potential-side power from a low-potential-side power supply and drain supplies the low-potential-side power to the precharge circuit.   
     
     
         9 . The semiconductor storage device as claimed in  claim 6 , further comprises:
 an equalizing circuit for equalizing a voltage of the first bit line and a voltage of the second bit line.   
     
     
         10 . The semiconductor storage device as claimed in  claim 9 , wherein
 the equalizing circuit comprises a fifth transistor of which source and drain are connected to the first bit line and the second bit line respectively, and   gates of the first transistor, the second transistor, and fifth transistor are controlled by a common control signal.