Wiring structure in a semiconductor device, method of forming the wiring structure, semiconductor device including the wiring structure and method of manufacturing the semiconductor device

Abstract

A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.

1 . A method of forming a semiconductor device, comprising:
 forming a first insulation layer on a substrate;   forming a first opening through the first insulation layer, wherein the first opening exposes a contact region of the substrate;   forming a first contact plug within the first opening and on the contact region, the first contact plug partially filling the first opening;   forming a preliminary capping layer pattern within the first opening and on the first contact plug;   forming a second insulation layer on the preliminary capping layer pattern and on the first insulation layer;   partially removing the second insulation layer and the preliminary capping layer pattern to form a capping layer pattern and a second opening exposing the first contact plug; and   forming a second contact plug within the second opening and on the first contact plug.   
     
     
         2 . The method of  claim 1 , wherein forming the first contact plug comprises:
 forming a conductive layer on the first insulation layer and within the first opening; and   partially removing the conductive layer.   
     
     
         3 . The method of  claim 1 , wherein forming the preliminary capping layer pattern comprises:
 forming a capping layer on the first insulation layer within the first opening; and   partially removing the capping layer until the first insulation layer is exposed.   
     
     
         4 . The method of  claim 1 , wherein forming the second contact plug comprises:
 forming a barrier metal layer on the first contact plug and on a sidewall of the second opening; and   forming a metal layer on the barrier metal layer within the second opening.   
     
     
         5 . The method of  claim 4 , wherein forming the second contact plug further comprises forming a metal silicide layer between the first contact plug and the barrier metal layer. 
     
     
         6 . The method of  claim 5 , further comprising simultaneously forming the barrier metal layer and the metal silicide layer. 
     
     
         7 . The method of  claim 1 , wherein a height of the first contact plug is in a range of about 60 to about 90 percent of a depth of the first opening. 
     
     
         8 . The method of  claim 7 , wherein an upper surface of the capping layer pattern is substantially coplanar with an upper surface of the first insulation layer. 
     
     
         9 . The method of  claim 7 , wherein an upper surface of the capping layer pattern is below an upper surface of the first insulation layer. 
     
     
         10 . The method of  claim 1 , wherein the capping layer pattern comprises an insulation material having an etching selectivity with respect to the first insulation layer. 
     
     
         11 . A method of manufacturing a semiconductor device, comprising:
 forming a first impurity region and a second impurity region at upper portions of a substrate;   forming a first insulating interlayer on the substrate;   forming a first opening and a second opening through the first insulating interlayer to expose the first impurity region and the second impurity region, respectively;   forming a preliminary first contact structure including a first contact plug and a preliminary first capping layer pattern in the first opening;   forming a preliminary second contact structure including a second contact plug and a preliminary second capping layer pattern in the second opening;   forming a second insulating interlayer on the first insulating interlayer and the preliminary first and the preliminary second capping layer patterns;   forming a first contact structure including the first contact plug and a first capping layer pattern by forming a third opening passing through the second insulating interlayer and the preliminary first capping layer pattern to expose the first contact plug;   forming a bit line electrically connected to the first contact plug in the third opening;   forming a third insulating interlayer on the second insulating interlayer to cover the bit line;   forming a second contact structure including the second contact plug and a second capping layer pattern by forming a fourth opening passing through the third insulating interlayer and the preliminary second capping layer pattern to expose the second contact plug; and   forming a storage node contact plug electrically connected to the second contact plug in the fourth opening.   
     
     
         12 . The method of  claim 11 , further comprising simultaneously forming the preliminary first contact structure and the preliminary second contact structure. 
     
     
         13 . The method of  claim 11 , wherein forming the preliminary first and the preliminary second contact structures comprises:
 forming a conductive layer on the first insulating interlayer within the first and the second openings;   partially removing the conductive layer to form the first and the second contact plugs;   forming an insulation layer on the first insulating interlayer and the first and the second contact plugs; and   partially removing the insulation layer to form the preliminary first and the preliminary second capping layer patterns.   
     
     
         14 . The method of  claim 11 , further comprising simultaneously forming the first contact structure and the second contact structure. 
     
     
         15 . The method of  claim 11 , wherein forming the bit line comprises:
 forming a bit line contact structure on the first contact plug and the second insulating interlayer to fill the third opening;   forming a bit line mask on the bit line contact structure; and   forming a bit line spacer on sidewalls of the bit line contact structure and the bit line mask.   
     
     
         16 . The method of  claim 15 , wherein forming the bit contact structure comprises:
 forming a barrier metal layer on the first contact plug, a sidewall of the third opening and the second insulating interlayer; and   forming a metal layer on the barrier metal layer.   
     
     
         17 . The method of  claim 16 , wherein forming the bit line contact structure further comprises forming a metal silicide layer between the first contact plug and the barrier metal layer. 
     
     
         18 . The method of  claim 11 , wherein forming the fourth opening comprises:
 anisotropically etching the third insulating interlayer and the second insulating interlayer by a self-alignment process; and   partially etching the preliminary second capping layer pattern by an anisotropic etching process.   
     
     
         19 . The method of  claim 18 , wherein forming the fourth opening further comprises enlarging a lower portion of the fourth opening by an isotropic etching process after anisotropically etching the second insulating interlayer and the third insulating interlayer. 
     
     
         20 . The method of  claim 19 , wherein enlarging a lower portion of the fourth opening comprises a wet etching process using an etching solution comprising an ammonium fluoride (NHF 4 ) solution, a hydrogen fluoride (HF) solution and deionized water. 
     
     
         21 . The method of  claim 11 , wherein a height of at least one of the first and the second contact plugs is in a range of about 60 to about 90 percent of the thickness of the first insulating interlayer. 
     
     
         22 . The method of  claim 21 , wherein an upper surface of at least one of the first and the second capping layer patterns is substantially coplanar with an upper surface of the first insulating interlayer. 
     
     
         23 . The method of  claim 21 , wherein an upper surface of at least one of the first and the second capping layer patterns is below an upper surface of the first insulating interlayer. 
     
     
         24 . The method of  claim 11 , wherein at least one of the first and the second capping layer patterns comprises an insulating material having an etching selectivity with respect to the first insulating interlayer.