US2011201156A1PendingUtilityA1
Method of manufacturing wafer level package including coating resin over the dicing lines
Est. expiryDec 19, 2028(~2.4 yrs left)· nominal 20-yr term from priority
H10W 74/00H10W 76/47H10W 74/114H10W 72/0198H10W 74/014H10P 95/00H10P 54/00
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Claims
Abstract
A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units.
Claims
exact text as granted — not AI-modified1 . A method of manufacturing a wafer level package comprising:
preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; and cutting a wafer level package along the dicing lines coated with the resin into units.
2 . The method of claim 1 , wherein the resin is formed of any one of transparent photocurable, thermosetting, and thermoplastic resin in the coating the resin on the dicing lines.Join the waitlist — get patent alerts
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