Semiconductor Memory Device Suitable for Mounting on a Portable Terminal

Abstract

A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect column access processing on column(s). The control being performed in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal. the control is also performed in synchronization with a second or later clock defined by a latency, to effect the column access processing on a second number of the columns remaining in the burst mode access

1 . A semiconductor memory device for operating in synchronization with a clock, performing access in a burst mode, and obtaining row and column addresses prior to production of a read signal or a write signal, comprising:
 a memory array having a plurality of memory cells arranged in rows and columns; and   a control circuit performing control, in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal, to effect row access processing on a selected row and to effect column access processing on column(s) starting from a first position and being equal in number to a first number exceeding zero and not exceeding a burst length, and   performing control, in synchronization with a second or later clock defined by a latency, to effect the column access processing on a second number of the columns remaining in the burst mode access.   
     
     
         2 . The semiconductor memory device according to  claim 1 , further comprising:
 a sense amplifier circuit amplifying a potential on a bit line pair connected to said memory cells; and   a column decoder selecting said column, wherein   said control circuit includes:   a first control circuit producing a column enable signal in accordance with a row activating signal being activated in synchronization with said first clock according to timing following production of a signal activating said sense amplifier, and   a second control circuit providing a first instructing signal activating said first number of columns to said column decoder in accordance with said column enable signal, and providing a second instructing signal activating said second number of columns to said column decoder in synchronization with said second clock or a later clock.   
     
     
         3 . The semiconductor memory device according to  claim 2 , wherein
 said control circuit includes a circuit producing a signal externally notifying of first timing data provided after column access processing synchronized with said first clock.   
     
     
         4 . The semiconductor memory device according to  claim 2 , wherein
 said control circuit includes a circuit externally notifying of timing of first data provided by performing column access processing in synchronization with said second clock or the later clock.   
     
     
         5 . The semiconductor memory device according to  claim 2 , further comprising:
 a shift circuit operating, as said first clock, a clock immediately following end of execution of a refresh operation, a read operation or a write operation when said read or write request signal is produced during the execution of said refresh, read or write operation.   
     
     
         6 . A semiconductor memory device being set to one of a plurality of operation modes according to a combination of external signals, and comprising:
 a memory array having a plurality of memory cells arranged in rows and columns;   bit line pairs connected to the memory cells;   a first amplifier circuit amplifying a potential on said bit line pair;   an I/O line pair connected to said plurality of bit line pairs; and   two or more kinds of second amplifier circuits being selectively activated in accordance with said mode for amplifying the potential on said I/O line pair.   
     
     
         7 . The semiconductor memory device according to  claim 6 , wherein
 said plurality of operation modes include a synchronous operation mode synchronous with an externally applied clock and an asynchronous operation mode asynchronous to the clock; and   said second amplifier circuit includes:   a first kind of amplifier circuit corresponding to the synchronous operation mode, and   a second kind of amplifier circuit corresponding to the asynchronous operation mode.   
     
     
         8 . The semiconductor memory device according to  claim 7 , further comprising:
 a control circuit setting said first and second kinds of amplifier circuits to the active and inactive states, respectively, when the synchronous mode is set, and setting said first and second kinds of amplifier circuits to the inactive and active states, respectively, when the asynchronous mode is set; and   a data bus driver connected to outputs of said first and second kinds of amplifier circuits, and providing either an output of said first kind of amplifier circuit or an output of said second kind of amplifier circuit onto a data bus.   
     
     
         9 . The semiconductor memory device according to  claim 8 , wherein
 said first kind of amplifier circuit includes a switch unit disconnecting said I/O line pair from an amplifier unit in said first kind of amplifier circuit based on a signal synchronized with the clock, and   said second kind of amplifier does not include a switch unit disconnecting said I/O line pair from an amplifier unit in said second kind of amplifier circuit.   
     
     
         10 . The semiconductor memory device according to  claim 7 , wherein
 said first and second kinds of amplifier circuits connected to said I/O line pair are aligned in a column direction, and   said I/O line pair is connected to said first and second kinds of amplifier circuits without diverging.   
     
     
         11 . A semiconductor memory device operable in synchronization with a clock, comprising:
 a memory array having a plurality of memory cells arranged in rows and columns;   a byte mask control circuit receiving an externally applied byte mask signal, and controlling byte mask processing based on said byte mask signal; and   an output circuit receiving data provided from said memory cell, and not outputting a byte corresponding to said byte mask signal of the data provided from said memory cell, wherein   when said byte mask control circuit receives the externally applied byte mask signal during row access processing performed for change to a second row due to reaching a last column in a first row during an operation of continuously effecting writing or reading on the first row and the subsequent second row, said byte mask control circuit defers mask processing to be effected on the byte corresponding to said byte mask signal until data of a next bit is output after the end of said row access.   
     
     
         12 . The semiconductor memory device according to  claim 11 , further comprising:
 a wait control circuit outputting a wait signal externally notifying that waiting is performed until output of data while the row access processing is being performed for the change to the next row;   said byte mask control circuit includes, for each byte:   a first circuit providing a signal produced based on said byte mask signal without disabling an output enable signal corresponding to said byte in such a case that said byte mask signal indicates that the byte mask is to be effected on the bit other than the leading bit to be subjected to said continuous reading or writing, and particularly in such a case that said wait signal is issued according to timing of output of said bit from said output circuit while the row access processing for change to said next row is not to be performed, and   a second circuit receiving and holding a signal produced based on said byte mask signal for disabling the output enable signal corresponding to said byte according to timing of releasing of said wait signal; and   when said output enable signal indicates “disable”, said output circuit does not provide the byte, corresponding to said output enable signal indicating the “disable”, of the data provided from said memory cell.   
     
     
         13 . A semiconductor memory device having a synchronous mode for operation synchronous with a clock and an asynchronous mode for operation asynchronous to the clock, comprising:
 a memory array having a plurality of memory cells arranged in rows and columns;   a setting circuit capable of setting one of a synchronous-fixed mode, an asynchronous-fixed mode and a synchronous/asynchronous mixed mode;   an asynchronous-changing circuit determining in said mixed mode whether a time from asserting of an external chip enable signal to rising of an external clock is equal to or greater than a predetermined value or not, and changing the mode to the asynchronous-fixed mode when the time is equal to or greater than said predetermined value;   a synchronous control circuit controlling a synchronous operation when the synchronous-fixed mode or the mixed mode is set; and   an asynchronous control circuit controlling the asynchronous operation when the asynchronous-fixed mode or the mixed mode is set, or when the mode is changed to the asynchronous-fixed mode, wherein   said asynchronous-changing circuit is deactivated in accordance with an output of the setting circuit.   
     
     
         14 . The semiconductor memory device according to  claim 13 , wherein
 said setting circuit is predetermined two bits in a bus configuration register, and   said asynchronous-changing circuit stops processing for said changing when a value of said bits indicates the synchronous-fixed mode and the asynchronous-fixed mode.   
     
     
         15 . A semiconductor memory device operable in synchronization with a clock comprising:
 a memory array having a plurality of memory cells arranged in rows and columns;   a chip enable buffer receiving an external chip enable signal, and producing an internal chip enable signal;   a clock buffer receiving an external clock and producing an internal clock;   an address buffer receiving an external address signal and producing an internal address signal; and   a control buffer receiving an external control signal other than the external chip enable signal and producing an internal control signal, wherein   said clock buffer, said address buffer and said control buffer receive said internal chip enable signal, and stop operations when said internal chip enable signal indicates deactivation of the chip;   said clock buffer, said address buffer and said control buffer execute the operations when said internal chip enable signal indicates activation;   said control buffer receives an external address take-in signal, and produces an internal address take-in signal;   said semiconductor memory device further comprising:   a delay circuit delaying said internal address take-in signal by a predetermined delay amount,   a data holding circuit holding an output of said delay circuit in synchronization with the internal clock;   a logical circuit providing an AND signal obtained from an output of said data holding circuit and said internal clock;   a circuit activating a row address strobe signal based on a leading pulse of said AND signal; and   said predetermined delay amount of said delay circuit is determined such that the leading pulse of said AND signal is formed of an internal clock pulse produced from an external clock pulse rising during an active state of said external address take-in signal.   
     
     
         16 . A semiconductor memory device being set to one of a plurality of operation modes, the semiconductor memory device comprising:
 a memory array having a plurality of memory cells arranged in rows and columns;   bit line pairs connected to the memory cells;   a first amplifier circuit amplifying a potential on said bit line pair;   an I/O line pair connected to said plurality of bit line pairs; and   two or more different types of second amplifier circuits connected to said I/O line pair and aligned in a column direction and wherein said I/O line pair connects said two or more different types of second amplifier circuits to one another.   
     
     
         17 . The semiconductor memory device according to  claim 16 , wherein a first type of second amplifier is arranged in a first region and a second type of second amplifier is arranged in a second region. 
     
     
         18 . The semiconductor memory device according to  claim 16 , wherein a first type of second amplifier circuit is a synchronous-compatible preamplifier and a second type of second amplifier is an asynchronous-compatible preamplifier. 
     
     
         19 . The semiconductor memory device according to  claim 16 , wherein said two or more different types of second amplifier circuits are serially connected via said I/O line pair. 
     
     
         20 . A semiconductor memory device being set to one a plurality of operation modes said semiconductor memory device comprising:
 a memory array having a plurality of memory cells arranged in rows and columns;   bit line pairs connected to memory cells;   a first amplifier circuit amplifying a potential on said bit line pair;   an I/O line pair connected to said plurality of bit line pairs;   two or more different types of second amplifier circuits connected to each I/O line pair and aligned in a row direction.   
     
     
         21 . The semiconductor memory device according to  claim 20 , wherein said I/O line pair has divergent portions which are connected to said two or more different types of second amplifier circuits, respectively. 
     
     
         22 . The semiconductor memory device according to  claim 20 , wherein a first type of second amplifier circuit is a synchronous-compatible preamplifier and a second type of second amplifier circuit is an asynchronous-compatible preamplifier. 
     
     
         23 . The semiconductor memory device according to  claim 20 , wherein said two or more different types of second amplifier circuits are arranged in a synchronous/asynchronous-compatible preamplifier arrangement region.