Semiconductor integrated circuit and data processing system

Abstract

An arrangement for detecting local light irradiation in an illegal attack attempt to intentionally induce a malfunction or faulty condition is formed on a small chip occupancy area so as to provide high detection sensitivity. In a region containing a logic circuit, a plurality of series-coupled detection inverters are distributively disposed as photodetector elements having a constant logical value of primary-stage input. When at least one of the series-coupled detection inverters is irradiated with light, an output thereof is inverted, thereby producing a final output through the series-coupled detection inverters. Based on the final output thus produced, local light irradiation can be detected.

1 . A semiconductor integrated circuit having a semiconductor chip, comprising:
 a logic circuit;   a plurality of series-coupled detection inverters that are distributively disposed in a region containing the logic circuit and are arranged to have a constant logical value of primary-stage input;   a detection circuit for detecting an input logical value inversion due to an output inversion of the detection inverter at the time of light irradiation; and   a limiter circuit for imposing limitation on operation of the logic circuit in response to the input logical value inversion detected by the detection circuit,   the logic circuit, the series-coupled detection inverters, the detection circuit, and the limiter circuit being formed in the single semiconductor chip.   
     
     
         2 . The semiconductor integrated circuit according to  claim 1 ,
 wherein each of the detection inverters comprises a CMOS inverter element, and either one of a NAND gate having all inputs thereof coupled in common and a NOR gate having all inputs thereof coupled in common.   
     
     
         3 . The semiconductor integrated circuit according to  claim 1 ,
 wherein a first resistor element is disposed on the power supply terminal side of a detection inverter that outputs a high level in a state prior to light irradiation.   
     
     
         4 . The semiconductor integrated circuit according to  claim 3 ,
 wherein a first semiconductor region containing a high-level-output transistor formed in the detection inverter that outputs a high level in a state prior to light irradiation is isolated from a second semiconductor region containing a transistor formed in the logic circuit and having a characteristic of the same conduction type as that of the first semiconductor region, and   wherein, through the first resistor element, a power supply voltage is applied to the first semiconductor region from a power feeding path extending in the second semiconductor region.   
     
     
         5 . The semiconductor integrated circuit according to  claim 1 ,
 wherein a second resistor element is disposed on the ground terminal side of a detection inverter that outputs a low level in a state prior to light irradiation.   
     
     
         6 . The semiconductor integrated circuit according to  claim 5 ,
 wherein a third semiconductor region containing a low-level-output transistor formed in the detection inverter that outputs a low level in a state prior to light irradiation is isolated from a fourth semiconductor region containing a transistor formed in the logic circuit and having a characteristic of the same conduction type as that of the third semiconductor region, and   wherein, through the second resistor element, a ground voltage is applied to the third semiconductor region from a power feeding path extending in the fourth semiconductor region.   
     
     
         7 . The semiconductor integrated circuit according to  claim 1 ,
 wherein a buffer inverter is disposed between the detection inverters, and   wherein a logical threshold voltage of the buffer inverter located at a stage posterior to the detection inverter that outputs a high level in a state prior to light irradiation is set to be higher than a logical threshold voltage of the inverter included in the logic circuit.   
     
     
         8 . The semiconductor integrated circuit according to  claim 1 ,
 wherein a buffer inverter is disposed between the detection inverters, and   wherein a logical threshold voltage of the buffer inverter located at a stage posterior to the detection inverter that outputs a low level in a state prior to light irradiation is set to be lower than a logical threshold voltage of the inverter included in the logic circuit.   
     
     
         9 . The semiconductor integrated circuit according to  claim 1 ,
 wherein a series circuit of the inverters and a detection circuit are disposed individually in each of partial circuit regions of the logic circuit, and   wherein the series circuit of the inverters and the detection circuit disposed in each partial circuit region are coupled so as to provide a form of coupling between mutually different circuit regions.   
     
     
         10 . The semiconductor integrated circuit according to  claim 9 , further comprising:
 a plurality of memory devices to be used by the logic circuit,   wherein the logic circuit includes a plurality of data processing units for carrying out data processing operations by using information held in the memory devices.   
     
     
         11 . A data processing system comprising:
 a plurality of semiconductor integrated circuits mounted over a circuit board,   wherein at least one of the semiconductor integrated circuits is arranged to have a logic circuit including a plurality of data processing units for carrying out data processing operations, and   wherein the at least one of the semiconductor integrated circuits comprises: a plurality of series-coupled detection inverters that are distributively disposed in a region containing the logic circuit and are arranged to have a constant logical value of primary-stage input; a detection circuit for detecting an input logical value inversion due to an output inversion of the detection inverter at the time of light irradiation; and a limiter circuit for imposing limitation on operation of the logic circuit in response to the input logical value inversion detected by the detection circuit.   
     
     
         12 . A semiconductor integrated circuit having a semiconductor chip, comprising:
 a logic circuit;   a plurality of series-coupled buffers that are distributively disposed in a region containing the logic circuit and are arranged to have a constant logical value of primary-stage input;   a plurality of parallel-coupled detection diodes that are in a reverse-biased state with respect to a signal path between an input of each of the buffers and an output of a buffer located at a stage anterior thereto;   a detection circuit for detecting an input logical value inversion due to a change to a forward-biased state in the detection diode at the time of light irradiation; and   a limiter circuit for imposing limitation on operation of the logic circuit in response to the input logical value inversion detected by the detection circuit,   the logic circuit, the series-coupled buffers, the parallel-coupled detection diodes, the detection circuit, and the limiter circuit being formed in the single semiconductor chip.   
     
     
         13 . The semiconductor integrated circuit according to  claim 12 ,
 wherein the logic circuit and the detection diode are formed in a semiconductor region having a predetermined height dimension in which a p-type well region receiving power from a ground line is in juxtaposition with an n-type well region receiving power from a power supply line,   wherein, with the cathode of the detection diode coupled to the signal path and the anode thereof coupled to the ground line, a p-type well region containing the detection diode is enlarged as compared with the height dimension of a p-type well region containing the logic circuit, and   wherein an n-type semiconductor region having a pn junction with the enlarged p-type well region is configured as a cathode.   
     
     
         14 . The semiconductor integrated circuit according to  claim 13 ,
 wherein a p-type semiconductor region corresponding to a ground line, from which power feeding is applied to the p-type well region containing the detection diode, is arranged to protrude toward the opposing side of the n-type semiconductor region configuring the cathode.   
     
     
         15 . The semiconductor integrated circuit according to  claim 13 ,
 wherein a silicide area for coupling the n-type semiconductor region containing the pn junction to a metallic layer corresponding to the signal path is formed limitedly in a peripheral part of a contact hole between the n-type semiconductor region and the metallic layer.   
     
     
         16 . The semiconductor integrated circuit according to  claim 12 ,
 wherein the logic circuit and the detection diode are formed in a semiconductor region having a predetermined height dimension in which a p-type well region receiving power from a ground line is in juxtaposition with an n-type well region receiving power from a power supply line,   wherein, with the anode of the detection diode coupled to the signal path and the cathode thereof coupled to the power supply line, the n-type well region containing the detection diode is enlarged as compared with the height dimension of an n-type well region containing the logic circuit, and   wherein a p-type semiconductor region having a pn junction with the enlarged n-type well region is configured as an anode.   
     
     
         17 . The semiconductor integrated circuit according to  claim 16 ,
 wherein the n-type semiconductor region corresponding to a power supply line, from which power feeding is applied to the n-type well region containing the detection diode, is arranged to protrude toward the opposing side of the p-type semiconductor region configuring the anode.   
     
     
         18 . The semiconductor integrated circuit according to  claim 17 ,
 wherein a silicide area for coupling the p-type semiconductor region containing the pn junction to a metallic layer corresponding to the signal path is formed limitedly in a peripheral part of a contact hole between the p-type semiconductor region and the metallic layer.   
     
     
         19 . The semiconductor integrated circuit according to  claim 13 ,
 wherein, with the cathode of the detection diode coupled to the signal path and the anode thereof coupled to the ground line, the buffer is configured of primary-stage and posterior-stage inverters coupled in series, and   wherein a logical threshold voltage of the primary-stage inverter is set to be higher than that of the posterior-stage inverter, and a power current feeding capacity of the posterior-stage inverter is set to be smaller than that of the primary-stage inverter.   
     
     
         20 . The semiconductor integrated circuit according to  claim 13 ,
 wherein, with the anode of the detection diode coupled to the signal path and the cathode thereof coupled to the power supply line, the buffer is configured of primary-stage and posterior-stage inverters coupled in series, and   wherein a logical threshold voltage of the primary-stage inverter is set to be lower than that of the posterior-stage inverter, and a ground current feeding capacity of the posterior-stage inverter is set to be smaller than that of the primary-stage inverter.   
     
     
         21 . The semiconductor integrated circuit according to  claim 12 ,
 wherein a series circuit of the buffers and diodes, and a detection circuit are disposed individually in each of partial circuit regions of the logic circuit, and   wherein the series circuit of the buffers and inverters, and the detection circuit disposed in each partial circuit region are coupled so as to provide a form of coupling between mutually different circuit regions.   
     
     
         22 . The semiconductor integrated circuit according to  claim 12 , further comprising:
 a plurality of memory devices to be used by the logic circuit,   wherein the logic circuit includes a plurality of data processing units for carrying out data processing operations by using information held in the memory devices.   
     
     
         23 . A data processing system comprising:
 a plurality of semiconductor integrated circuits mounted over a circuit board,   wherein at least one of the semiconductor integrated circuits is arranged to have a logic circuit including a plurality of data processing units for carrying out data processing operations, and   wherein the at least one of the semiconductor integrated circuits comprises: a plurality of series-coupled buffers that are distributively disposed in a region containing the logic circuit and are arranged to have a constant logical value of primary-stage input; a plurality of parallel-coupled detection diodes that are in a reverse-biased state with respect to a signal path between an input of each of the buffers and an output of a buffer located at a stage anterior thereto; a detection circuit for detecting an input logical value inversion due to a change to a forward-biased state in the detection diode at the time of light irradiation; and a limiter circuit for imposing limitation on operation of the logic circuit in response to the input logical value inversion detected by the detection circuit.