Methods of fabricating nonvolatile memory devices having stacked structures

Abstract

A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

1 . A method of fabricating a memory cell, the method comprising:
 forming a stack of layers including at least two semiconductor layers with at least one sacrificial layer therebetween;   forming spaced-apart trench isolation regions, each extending through the stack of layers;   patterning the stack of layers to form a stack of patterns including at least two semiconductor patterns and at least one sacrificial pattern therebetween and spaced-apart first and second recesses disposed at respective sides of the stack of patterns and bounded by the trench isolation regions;   forming first and second source/drain regions in respective ones of the first and second recesses;   removing portions of the trench isolation regions on respective third and fourth sides of the stack of patterns to expose a sacrificial pattern of the stack of patterns at first and second ends thereof;   removing the exposed sacrificial pattern to form a passage between first and second semiconductor patterns of the stack of patterns;   forming a first gate structure in the passage; and   forming a second gate structure overlying the first gate structure on an upper one of the first and second semiconductor patterns,   wherein the first semiconductor pattern comprises a portion of the substrate protruding between the first and second source/drain regions.   
     
     
         2 . The method of  claim 1 , wherein forming a stack of layers comprises alternately forming single crystal semiconductor layers of first and second types by epitaxial growth. 
     
     
         3 . The method of  claim 2 , wherein alternately forming single crystal semiconductor layers of first and second types by epitaxial growth comprises alternately forming single silicon-germanium and silicon layers. 
     
     
         4 . The method of  claim 1 , wherein patterning the stack of layers comprises:
 forming an elongate gate mask region on the stack of layers, the gate mask region extending transverse to the trench isolation regions;   etching the stack of layers using the gate mask region as an etching mask.   
     
     
         5 . The method of  claim 4 , wherein the gate mask region comprises a dummy gate structure. 
     
     
         6 . The method of  claim 1 , wherein forming first and second source/drain regions comprises forming respective first and second single crystal semiconductor regions in the respective first and second recesses by epitaxial growth. 
     
     
         7 . The method of  claim 1 , wherein forming first and second source/drain regions comprises forming first and second subregions in each of the first and second source drain regions adjacent respective ones of the second gate structure and the first gate structure, the first subregion having a first impurity concentration and the second subregion having a second impurity concentration. 
     
     
         8 . The method of  claim 7 , wherein the first and second subregions are formed by ion implantation and/or in situ doping. 
     
     
         9 . The method  claim 1 , wherein removing portions of the trench isolation regions on respective third and fourth sides of the stack of patterns comprises:
 forming respective first and second mask regions on respective sides of the gate mask region, the first and second mask regions covering respective ones of first and second source/drain regions and adjacent portions of the trench isolation regions;   removing the gate mask region; and   etching using the first and second mask regions as a mask to remove the portions of the trench isolation regions on the respective third and fourth sides of the stack of patterns and thereby expose the respective first and second ends of the sacrificial pattern of the stack of patterns.   
     
     
         10 . The method of  claim 1 , wherein removing the exposed sacrificial pattern to form a passage between first and second semiconductor patterns of the stack of patterns comprises wet etching the exposed sacrificial pattern. 
     
     
         11 . The method of  claim 1 , wherein forming a first gate structure in the passage comprises:
 forming a tunnel oxide layer on walls of the passage;   forming a charge trap layer on the tunnel oxide layer;   forming a dielectric layer on the charge trap layer;   forming a conductive gate electrode layer on the dielectric layer to a thickness sufficient to fill the passage.   
     
     
         12 . The method of  claim 1 , wherein forming a second gate structure on an upper one of the first and second semiconductor patterns overlying the first gate structure comprises:
 removing portions of the conductive gate electrode layer, the dielectric layer, the charge trap layer, and the tunnel oxide layer to expose the first and second mask regions, the upper one of the first and second semiconductor patterns and the first gate structure through spaced-apart recesses in the trench isolation regions;   forming backfilled insulation regions in the recesses in the trench isolation regions; and   forming a second gate structure on the upper one of the first and second semiconductor patterns and the backfilled insulation regions.   
     
     
         13 . The method  claim 12 , wherein forming a second gate structure on the upper one of the first and second semiconductor patterns and the backfilled insulation regions comprises:
 sequentially forming a tunnel oxide layer, a charge trap layer, a dielectric layer and a conductive gate electrode layer; and   patterning the tunnel oxide layer, the charge trap layer, the dielectric layer and the conductive gate electrode layer to form the second gate structure.   
     
     
         14 . The method of  claim 1 , wherein forming a second gate structure overlying the first gate structure on an upper one of the first and second semiconductor patterns comprises forming the second gate electrode structure such that a portion of the first gate structure extends beyond an end of the second gate structure, and wherein the method further comprises:
 forming an interlayer dielectric (ILD) layer covering the second gate structure; and   forming a conductive wiring structure disposed on the ILD layer and having a contact plug extending through the ILD layer to contact the portion of the first gate structure that extends beyond the end of the second gate structure.   
     
     
         15 . The method of  claim 1 , further comprising forming a third gate structure underlying a lower one of the first and second semiconductor patterns. 
     
     
         16 . The method of  claim 15 :
 wherein forming a stack of layers is preceded by forming a doped control gate region in the substrate;   wherein forming a stack of layers comprises forming a stack of layers including at least two semiconductor layers and at least two sacrificial layers including a lower sacrificial layer most adjacent the doped control gate region;   wherein patterning the stack of layers to form a stack of patterns comprises patterning some of the stack of layers to form a stack of patterns on the lower sacrificial layer and overlying the doped control gate region, the stack of layers including at least two semiconductor patterns and at least one sacrificial pattern therebetween, and to form spaced-apart first and second recesses at respective sides of the stack of patterns and bounded by the trench isolation regions and the lower sacrificial layer;   wherein forming first and second source/drain regions in respective ones of the first and second recesses comprises forming first and second source/drain regions in respective ones of the first and second recesses and on the lower sacrificial layer;   wherein removing portions of the trench isolation regions on respective third and fourth sides of the stack of patterns to expose a sacrificial pattern of the stack of patterns at first and second ends thereof comprises removing portions of the trench isolation regions on respective third and fourth sides of the stack of patterns to expose a sacrificial pattern of the stack of patterns at first and second ends thereof and to expose the lower sacrificial layer;   wherein removing the exposed sacrificial pattern to form a passage between first and second semiconductor patterns of the stack of patterns comprises removing the exposed sacrificial pattern and a portion of the lower sacrificial layer to form a first passage between first and second semiconductor patterns of the stack of patterns and a second passage between a lower one of the first and second semiconductor patterns and the doped control gate region;   wherein forming a first gate structure comprises forming the first gate structure in the first passage; and   wherein the method further comprises forming a charge trap structure in the second passage.   
     
     
         17 . The method of  claim 16 , wherein forming a first gate structure in the first passage and forming a charge trap structure in the second passage comprises:
 forming a tunnel oxide layer in the first and second passages;   forming a charge trap layer on the tunnel oxide layer in the first and second passages;   forming a dielectric layer on the charge trap layer to a thickness sufficient to fill the second passage; and   forming a conductive gate electrode layer on the charge trap layer in the first passage to a thickness sufficient to fill the first passage.   
     
     
         18 . The method of  claim 16 , wherein forming first and second source/drain regions comprises forming first, second and third subregions in each of the first and second source drain regions adjacent respective ones of the second gate structure, the first gate structure and the doped control gate region, the first subregion having a first impurity concentration, the second subregion having a second impurity concentration and the third subregion having a third impurity concentration. 
     
     
         19 . A method of fabricating a memory cell, the method comprising:
 forming a doped control gate region in a substrate;   forming a stack of layers on the substrate, the stack of layers including at least two semiconductor layers and at least two sacrificial layers including a lower sacrificial layer most adjacent the doped control gate region;   forming spaced-apart trench isolation regions each extending through the stack of layers;   patterning some of the stack of layers to form a stack of patterns on the lower sacrificial pattern and overlying the doped control gate region, the stack of layers including at least two semiconductor patterns and at least one sacrificial pattern therebetween, and to form spaced-apart first and second recesses at respective sides of the stack of patterns and bounded by the trench isolation regions and the lower sacrificial layer;   forming first and second source/drain regions in respective ones of the first and second recesses and on the lower sacrificial layer;   removing portions of the trench isolation regions on respective third and fourth sides of the stack of patterns to expose a sacrificial pattern of the stack of patterns at first and second ends thereof and to expose the lower sacrificial layer;   removing the exposed sacrificial pattern and at least a portion of the lower sacrificial layer to form a first passage between first and second semiconductor patterns of the stack of patterns and a second passage between a lower one of the first and second semiconductor pattern and the doped control gate region;   forming a first gate structure in the first passage;   forming a charge trap structure in the second passage; and   forming a second gate structure overlying the first gate structure on an upper one of the first and second semiconductor patterns.