Resistive Memory Structure with Buffer Layer

Abstract

A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

1 . A method of fabricating a memory device, comprising:
 forming a first electrode and a second electrode; and   forming a memory element and a buffer layer located between and electrically coupled to the first and the second electrodes, the memory element comprising one or more metal oxygen compounds, the buffer layer comprising at least one of an oxide and a nitride.   
     
     
         2 . The method according to  claim 1 , wherein the buffer layer is formed by down-stream plasma, plasma sputtering or reactive sputtering. 
     
     
         3 . The method according to  claim 1 , wherein the memory element is formed by plasma oxidation or thermal oxidation. 
     
     
         4 . The method according to  claim 1 , wherein the buffer layer is located between and electrically coupled to the memory element and the first electrode. 
     
     
         5 . The method according to  claim 1 , wherein the buffer layer has a thickness of less than 50 Å. 
     
     
         6 . The method according to  claim 1 , wherein the buffer layer has a resistivity of about 10 13 ˜10 16  ohm-cm. 
     
     
         7 . The method according to  claim 4 , further comprising forming a second buffer layer located between and electrically coupled to the memory element and the second electrode, the second buffer layer comprising at least one of an oxide and a nitride. 
     
     
         8 . The method according to  claim 7 , wherein the second buffer layer has a thickness of less than 50 Å 
     
     
         9 . The method according to  claim 1 , wherein the memory element has a thickness, measured between the first and second electrodes, of 50-1000 Å. 
     
     
         10 . The method according to  claim 1 , wherein the memory element comprises at least one of the following: WO x , NiO, Nb 2 O 5 , CuO 2 , Ta 2 O 5 , Al 2 O 3 , CoO, Fe 2 O 3 , HfO 2 , TiO 2 , SrTiO 3 , SrZrO 3 , (BaSr)TiO 3 , GeTi, SnMnTe, SbTe, Pr 1-x Ca x MnO 3 , (Te—Cu/GdOX, GeSb with Ag +  or Cu + ). 
     
     
         11 . The method according to  claim 1 , wherein the buffer layer comprises at least one of the following: a tungsten oxide, a titanium oxide, an aluminum oxide, a zirconium oxide and a silicon nitride. 
     
     
         12 . The method according to  claim 1 , wherein the buffer layer comprises SiO 2 . 
     
     
         13 . A method for fabricating a memory device comprising:
 forming a first electrode and a second electrode;   forming a memory element and a buffer layer located between and electrically coupled to the first and the second electrodes;   selecting the memory element to comprise at least one of the following: WO x , NiO, Nb 2 O 5 , CuO 2 , Ta 2 O 5 , Al 2 O 3 , CoO, Fe 2 O 3 , HfO 2 , TiO 2 , GeTi, SnMnTe, SbTe, Pr 1-x Ca x MnO 3 , (Te—Cu/GdOX, GeSb with Ag +  or Cu) + ; and   selecting the buffer layer to comprise at least one of the following: a tungsten oxide, a titanium oxide, an aluminum oxide, a zirconium oxide and a silicon nitride.   
     
     
         14 . The method according to  claim 13 , wherein the buffer layer is located between and electrically coupled to the memory element and the first electrode. 
     
     
         15 . The method according to  claim 14 , further comprising a second buffer layer located between and electrically coupled to the memory element and the second electrode, the second buffer layer comprising at least one of an oxide and a nitride. 
     
     
         16 . The memory device according to  claim 13 , wherein the memory element is a programmable resistance memory element. 
     
     
         17 . A method of fabricating a memory device comprising:
 forming a first electrode;   forming a metal oxide resistive random access memory element located over and electrically coupled to the first electrode;   the memory element comprising at least one of the following: WO x , NiO, Nb 2 O 5 , CuO 2 , Ta 2 O 5 , Al 2 O 3 , CoO, Fe 2 O 3 , HfO 2 , TiO 2 , Pr 1-x Ca x MnO 3 , (Te—Cu/GdOX, GeSb with Ag +  or Cu + );   forming a buffer layer located over and electrically coupled to the memory element; and   forming a second electrode located over and contacting the buffer layer.   
     
     
         18 . The method according to  claim 17 , wherein the buffer layer has a resistivity of about 10 13 ˜10 16  ohm-cm. 
     
     
         19 . The method according to  claim 17 , further comprising forming a second buffer layer located between and electrically coupled to the memory element and the first electrode, the second buffer layer comprising at least one of an oxide and a nitride. 
     
     
         20 . The method according to  claim 19 , wherein the second buffer layer has a thickness of less than 50 Å. 
     
     
         21 . The method according to  claim 17 , wherein the memory element has a thickness, measured between the first and second electrodes, of 50-1000 Å. 
     
     
         22 . The method according to  claim 17 , further comprising selecting the buffer layer to comprise at least one of the following: a tungsten oxide, a titanium oxide, an aluminum oxide, a zirconium oxide, a silicon nitride and a titanium nitride. 
     
     
         23 . The method according to  claim 17 , further comprising selecting the buffer layer to comprise SiO 2 . 
     
     
         24 . The method according to  claim 17 , wherein the memory element is a programmable resistance random access memory element.