Electromechanical memory devices and methods of manufacturing the same

Abstract

In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction. The bit line is suspended between the first word line structure and the second word line structure such that the bit line deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position.

1 . A stacked memory device comprising:
 a first device layer including a first array of memory cells;   a second device layer including a second array of memory cells;   a third device layer including control circuitry for accessing the first array of memory cells and the second array of memory cells, the first, second and third device layers being vertically arranged with respect to each other,   to wherein the memory cells of the first array of memory cells and the second array of memory cells each include:
 a first word line structure; 
 a second word line structure spaced apart from the first word line structure; and 
 a bit line that extends over an upper surface of the first word line structure and below a lower surface of the second word line structure, the bit line being spaced apart from the first word line structure by a first gap and being spaced apart from the second word line structure by a second gap, the bit line being suspended between the first word line structure and the second word line structure. 
   
     
     
         2 . The stacked memory device of  claim 1  wherein the memory cells of the first array of memory cells are non-volatile memory cells and the memory cells of the second array of memory cells are volatile memory cells. 
     
     
         3 . The stacked memory device of  claim 1  wherein the memory cells of both the first array of memory cells and the second array of memory cells are volatile memory cells. 
     
     
         4 . The stacked memory device of  claim 1  wherein the memory cells of both the first array of memory cells and the second array of memory cells are non-volatile memory cells. 
     
     
         5 . The stacked memory device of  claim 1  wherein in each of the memory cells, the bit line comprises first and second portions that extend in a direction along sidewalls of the first word line structure and a third portion that extends in a direction along a top of the first word line structure between the first and second portions. 
     
     
         6 . The stacked memory device of  claim 5  wherein the first gap extends between the first and second portions of the bit line and the first word line structure and between the third portion of the bit line and the first word line structure. 
     
     
         7 . The stacked memory device of  claim 5  further comprising a dielectric layer on the substrate and the bit line, and wherein the second gap extends between the third portion of the bit line and the second word line structure and extends between the first and second portions of the bit line and the dielectric layer. 
     
     
         8 . The stacked memory device of  claim 5  wherein the second gap extends between the third portion of the bit line and the second word line structure. 
     
     
         9 . The stacked memory device of  claim 1  wherein, the bit line comprises an elastically deformable material. 
     
     
         10 . The stacked memory device of  claim 9  wherein the bit line comprises at least one material selected from the group consisting of: gold, silver, copper, aluminum, tungsten, TiN, conductive metal, shaped memory alloy, and nanotubes. 
     
     
         11 . The stacked memory device of  claim 1  wherein the memory cells of at least one of the array and second array comprise volatile memory cells and in the at least one array, the first word line structure and second word line structure each comprise a conductor. 
     
     
         12 . The stacked memory device of  claim 1  wherein in each of the memory cells, the bit line is suspended between the first word line structure and the second word line structure such that the bit line deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position. 
     
     
         13 . The stacked memory device of  claim 12  wherein the memory cells of at least one of the first array and second array comprise non-volatile memory cells, and in the memory cells of the at least one array, at least one of the first word line structure and the second word line structure comprises:
 a conductive layer; and 
 a charge trapping structure between the conductive layer and the bit line and spaced apart from the bit line by a corresponding one of the first and second gaps. 
 
     
     
         14 . The stacked memory device of  claim 13  wherein in at least one of the first bent position and second bent position, the bit line is capacitively coupled to the charge trapping structure of the corresponding at least one first word line structure and second word line structure. 
     
     
         15 . The stacked memory device of  claim 14  wherein in the at least one of the first bent position and second bent position, the bit line is further capacitively coupled to the conductive layer of the corresponding at least one first word line structure and second word line structure. 
     
     
         16 . The stacked memory device of  claim 13  wherein the charge trapping structure comprises a structure selected from the group consisting of: an oxide-nitride-oxide (ONO) structure and an oxide-nitride-alumina (ONA) structure. 
     
     
         17 . The stacked memory device of  claim 13  further comprising in the memory cells of the at least one array, a transition layer between the conductive layer and the charge trapping structure of the at least one of the first and second word line structures. 
     
     
         18 . The stacked memory device of  claim 13  wherein one of the first and second word line structures comprises a write word line structure and wherein another of the first and second word line structures comprises a read word line structure, and wherein, during a programming operation of the non-volatile memory device, the bit line is placed in one of the a bent position in contact with the write word line structure and the rest position, by applying a first voltage potential between the write word line structure and the bit line. 
     
     
         19 . The stacked memory device of  claim 18  wherein during a programming operation of a first state of the non-volatile memory device that results in the bit line being placed in a bent position in contact with the write word line structure, the bit line bends to make contact with the charge trapping structure of the write word line structure in the bent position in response to the first voltage potential between the write word line structure and the bit line, and wherein, when the first voltage potential between the write word line structure and the bit line is removed, the bit line remains in the bent position as a result of charge that is trapped in the charge trapping structure of the write word line structure. 
     
     
         20 . The stacked memory device of  claim 19  wherein during a read operation of the non-volatile memory device in the first state, a second voltage potential is applied between the bit line and the read word line structure, and wherein the read operation results in the determination of the first state when the bit line remains in the bent position in contact with the write word line structure, despite application of the second voltage potential. 
     
     
         21 . The stacked memory device of  claim 18  wherein during a programming operation of a second state of the non-volatile memory device that results in the bit line being placed in the rest position, the bit line is isolated from the charge trapping structure of the write word line structure in the rest position in response to the first voltage potential between the write word line structure and the bit line, and wherein, when the first voltage potential between the write word line structure and the bit line is removed, the bit line remains in the rest position. 
     
     
         22 . The stacked memory device of  claim 21  wherein during a read operation of the non-volatile memory device in the second state, a second voltage potential is applied between the bit line and the read word line structure, and wherein the read operation results in the determination of the second state when the bit line is placed in a bent position in contact with the read word line structure as a result of the applied second voltage potential.