Stack package

Abstract

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads to of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

1 . A stack package comprising:
 a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;   a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads; and   capacitors interposed between the first semiconductor chip and the second semiconductor chip, and having first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.   
     
     
         2 . The stack package according to  claim 1 , further comprising:
 first connection members electrically connecting the second pads of the first semiconductor chip and the fourth pads of the second semiconductor chip.   
     
     
         3 . The stack package according to  claim 1 , wherein the first pads comprise power pads and the third pads comprise ground pads, or the first pads comprise ground pads and the third pads comprise power pads. 
     
     
         4 . The stack package according to  claim 1 , wherein the first electrodes of the capacitors are electrically connected with the first pads of the first semiconductor chip through second connection members, and the second electrodes of the capacitors are electrically connected with the third pads of the second semiconductor chip through third connection members. 
     
     
         5 . The stack package according to  claim 1 , wherein the first electrodes and the second electrodes of the capacitors directly contact the first surface of the first semiconductor chip having the first pads disposed thereon and the third surface of the second semiconductor chip having the third pads disposed thereon, respectively. 
     
     
         6 . The stack package according to  claim 1 , wherein the first electrodes and the second electrodes of the capacitors have a shape of a plate. 
     
     
         7 . The stack package according to  claim 1 , wherein the first electrode of each capacitor includes a first plate part having a plurality of first projecting parts formed thereon extending toward the second electrode, and the second electrode of each capacitor includes a second plate part having a plurality of second projecting parts formed thereon so as to extend toward the first electrode between the first projecting parts. 
     
     
         8 . The stack package according to  claim 1 , wherein an area of a surface of each capacitor is less than an area of each of the first surface of the first semiconductor chip and an area of the third surface of the second semiconductor chip. 
     
     
         9 . The stack package according to  claim 8 , wherein the dielectrics of the capacitors are disposed only between the first electrodes and the second electrodes. 
     
     
         10 . The stack package according to  claim 8 , wherein the dielectrics of the capacitors are disposed in a space between the first semiconductor chip and the second semiconductor chip, including spaces between the first electrodes and the second electrodes. 
     
     
         11 . The stack package according to  claim 1 , wherein an area of a surface of each of the capacitors is the substantially equal to an area of each of the first surface of the first semiconductor chip and an area of the third surface of the second semiconductor chips, and an opening is defined in each of the capacitors through which a connection part connecting the second pad of the first semiconductor chip and the fourth pad of the second semiconductor chip passes. 
     
     
         12 . The stack package according to  claim 1 , further comprising:
 first redistribution lines disposed on the third surface of the second semiconductor chip including first ends electrically connected with the third pads and second ends extending to an edge of the third surface; and   second redistribution lines disposed on the third surface of the second semiconductor chip including first ends electrically connected with the fourth pads and the second ends extending to a second edge of the third surface opposite the first edge.   
     
     
         13 . The stack package according to  claim 12 , further comprising:
 a substrate having a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads connected with the first redistribution lines and second connection pads connected with the second redistribution lines, and a sixth surface facing away from the fifth surface and having third connection pads disposed thereon;   connection members connecting the second ends of the first redistribution lines with the first connection pads and the second ends of the second redistribution lines with the second connection pads;   an encapsulant sealing the fifth surface of the substrate, the first and second semiconductor chips, and the connection members; and   external mounting members attached to the third connection members of the substrate.   
     
     
         14 . The stack package according to  claim 1 , further comprising:
 through-electrodes formed in the second semiconductor chip passing through the third and fourth surfaces of the second semiconductor chip, and connected with the third pads and the fourth pads.   
     
     
         15 . The stack package according to  claim 14 , further comprising:
 a substrate having a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads and second connection pads connected with the through-electrodes, and a sixth surface facing away from the fifth surface having third connection pads disposed thereon;   an encapsulant sealing the fifth surface of the substrate and the first and second semiconductor chips; and   external mounting members attached to the third connection pads of the substrate.   
     
     
         16 . A stack package comprising:
 a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;   a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface which facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads;   connection members electrically connecting the first pads with the third pads and the second pads with the fourth pads;   a substrate including a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads and second connection pads, and a sixth surface facing away from the fifth surface and having third connection pads disposed thereon;   capacitors including first electrodes electrically connected with the third pads, second electrodes electrically connected with the first connection pads, and dielectrics interposed between the first electrodes and second electrodes; and   connection members connecting the fourth pads of the second semiconductor chip with the second connection pads of the substrate.   
     
     
         17 . The stack package according to  claim 16 , further comprising:
 first redistribution lines disposed on the third surface of the second semiconductor chip having first ends electrically connected with the third pads and second ends extending to a first edge of the third surface electrically connected with the first electrodes of the capacitors; and   second redistribution lines disposed on the third surface of the second semiconductor chip having first ends electrically connected with the fourth pads and second ends extending to a second edge of the third surface opposite the first edge, the second ends electrically connected with the second connection pads of the substrate.   
     
     
         18 . The stack package according to  claim 16 , further comprising:
 an encapsulant sealing the fifth surface of the substrate, the first and second semiconductor chips, and the capacitors; and   external mounting members attached to the third connection members of the substrate.   
     
     
         19 . A stack package comprising:
 a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;   a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface which facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads;   first redistribution lines disposed on the third surface of the second semiconductor chip having first ends connected with the first pads and the third pads, and second ends extending to a first side surface adjoining the third surface;   second redistribution lines disposed on the third surface of the second semiconductor chip having first ends connected with the second pads and the fourth pads, and second ends extending to a second side surface adjoining the third surface, the second side surface facing away from the first side surface;   a substrate including a fifth surface attached to the fourth surface of the second semiconductor chip having first connection pads and second connection pads disposed thereon, and a sixth surface facing away from the fifth surface having third connection pads disposed thereon;   capacitors including first electrodes connected with the second ends of the first redistribution lines extending to the first side surface of the second semiconductor chip, second electrodes connected with the first connection pads, and dielectrics interposed between the first electrodes and the second electrodes; and   connection members connecting the second ends of the second redistribution lines and the second connection pads of the substrate.   
     
     
         20 . The stack package according to  claim 19 , wherein the first redistribution lines directly contact the first pads and third pads and the second redistribution lines directly contact the second pads and fourth pads, and the first and second redistribution lines are electrically insulated from the first and second semiconductor chips.