US2011185327A1PendingUtilityA1

Delay calculating method in semiconductor integrated circuit

Assignee: PANASONIC CORPPriority: Dec 8, 2004Filed: Apr 1, 2011Published: Jul 28, 2011
Est. expiryDec 8, 2024(expired)· nominal 20-yr term from priority
G06F 30/3312
44
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.

Claims

exact text as granted — not AI-modified
1 . A delay calculating method in a semiconductor integrated circuit comprising:
 a function setting step in which a function for calculating an input pin capacitance of an instance constituting a cell constituting the semiconductor integrated circuit in a characterizing process of the cell and expressing a predetermined parameter in the form of an argument, is set per cell;   a parameter calculating step in which a delay library of each cell, a wire capacitance and an resistance of each cell, an initial value of the input pin capacitance of the cell and a cell connection information of the cell are inputted so as to calculate the parameter in each instance;   an input pin capacitance calculating step in which the argument including the parameter obtained in the parameter calculating step is assigned to the function set in the function setting step so as to calculate the input pin capacitance in each instance; and   a delay calculating step in which a delay is calculated by means of the input pin capacitance of the instance obtained in the input pin capacitance calculating step, wherein the calculation of the parameter in each instance is repeated whenever necessary.   
     
     
         2 - 17 . (canceled)

Join the waitlist — get patent alerts

Track US2011185327A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.