Controlling two jtag tap controllers with one set of jtag pins

Abstract

Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary scan circuit with a second plurality of control inputs, and a plurality of boundary scan control signals connected to the first plurality of control inputs on the first boundary scan circuit and to the second plurality of control inputs on the second boundary scan circuit. At least two of the plurality of boundary scan control signals are connected between the first boundary scan circuit and the second boundary scan circuit in a crossover fashion.

1 . An process of making an integrated circuit comprising:
 A. fabricating a semiconductor substrate to form integrated circuitry on the substrate, the integrated circuitry including a first test access port controller with a first mode input and a first clock input and a second test access port controller with a second mode input connected to the first clock input and a second clock input connected to the first mode input; and   B. testing the integrated circuitry to determine operability by:
 i. applying a clock signal to the first clock input and the second mode input, the clock signal having a series of rising edges; and 
 ii. applying a mode signal to the first mode input and the second clock input, the mode signal having a rising edge that is delayed in time after a rising edge of the clock signal. 
   
     
     
         2 . The process of  claim 1  in which the controllers include state machines operating in states that include a Test Logic Reset state, and the testing including maintaining the second test access port controller in the Test Logic Reset State. 
     
     
         3 . The process of  claim 1  in which the controllers include state machines operating in states that include a Test Logic Reset state, and the testing including maintaining the second test access port controller in the Test Logic Reset State and operating the first test access port controller in states other than the Test Logic Reset state. 
     
     
         4 . The process of  claim 1  in which the testing includes operating the first test access port controller through states of SELECT-DR, CAPTURE-DR, SHIFT-DR, EXIT 1 -DR, PAUSE-DR, EXIT 2 -DR, and UPDATE-DR.