Display element drive circuit and display apparatus
Abstract
A display element drive circuit includes a first circuit which holds as a voltage component electric charges based on a gradation signal corresponding to display data, a second circuit which supplies the gradation signal to the electric charge holding circuit at a timing of application of a selection signal, current control type display elements, and a third circuit which generates a driving current based on the voltage component held in the first circuit and supplies the generated driving current to the display element. One of the second and third circuits includes at least one field effect transistor. The field effect transistor includes gate, source and drain electrodes, and a source-side parasitic capacitance formed between the gate and source electrodes and a drain-side parasitic capacitance formed between the gate and drain electrodes of the field effect transistor have different capacitance values.
Claims
exact text as granted — not AI-modified1 . A display element drive circuit comprising:
a current control type display element; a driving current control circuit which has a gradation signal corresponding to display data supplied thereto, generates a driving current based on the gradation signal, and supplies the generated driving current to the display element; and a write control circuit which has a selection signal applied thereto, and supplies the gradation signal to the driving current control circuit, wherein: the write control circuit comprises a write transistor and a control transistor; the write transistor comprises a first gate electrode, a first source electrode, a first drain electrode, a first parasitic capacitance formed between (i) one of the first source electrode and the first drain electrode and (ii) the first gate electrode, and a second parasitic capacitance formed between (i) the other of the first source electrode and the first drain electrode and (ii) the first gate electrode; the selection signal is applied to the first gate electrode; said one of the first source electrode and the first drain electrode is connected to a signal line; said other of the first source electrode and the first drain electrode is connected to the driving current control circuit; a capacitance value of the first parasitic capacitance is smaller than a capacitance value of the second parasitic capacitance; the control transistor comprises a second gate electrode, a second source electrode, a second drain electrode, a third parasitic capacitance formed between (i) one of the second source electrode and the second drain electrode and (ii) the second gate electrode, and a fourth parasitic capacitance formed between (i) the other of the second source electrode and the second drain electrode and (ii) the second gate electrode; the selection signal is applied to the second gate electrode; a predetermined power supply voltage is applied to said one of the second source electrode and the second drain electrode; said other of the second source electrode and the second drain electrode is connected to the driving current control circuit; and the third parasitic capacitance and the fourth parasitic capacitance have capacitance values that are different from each other.
2 . The display element drive circuit according to claim 1 , wherein the capacitance value of the third parasitic capacitance is larger than the capacitance value of the fourth parasitic capacitance.
3 . The display element drive circuit according to claim 1 , wherein the capacitance value of the third parasitic capacitance is smaller than the capacitance value of the fourth parasitic capacitance.
4 . The display element drive circuit according to claim 1 , wherein:
the write transistor further comprises a first semiconductor layer; the first source electrode and the first drain electrode are provided on the first semiconductor layer; one side of the first source electrode and one side of the first drain electrode are spaced apart and opposite to each other on the first semiconductor layer; and a length of the one side of the one of the first source electrode and the first drain electrode is smaller than a length of the one side of the other of the first source electrode and the first drain electrode.
5 . The display element drive circuit according to claim 4 , wherein:
the first gate electrode has a circular arc strip-like planar shape; and the one side of the first source electrode and the one side of the first drain electrode have a circular arc shape.
6 . The display element drive circuit according to claim 4 , wherein:
the first gate electrode has a rectangular planar shape; and at least a portion of the one side of the first source electrode and at least a portion of the one side of the first drain electrode have a linear shape.
7 . The display element drive circuit according to claim 1 , wherein:
the control transistor further comprises a second semiconductor layer; the second source electrode and the second drain electrode are provided on the second semiconductor layer; one side of the second source electrode and one side of the second drain electrode are spaced apart and opposite to each other on the second semiconductor layer; and a length of the one side of the one of the second source electrode and the second drain electrode is different from a length of the one side of the other of the second source electrode and the second drain electrode.
8 . The display element drive circuit according to claim 7 , wherein:
the second gate electrode has a circular arc strip-like planar shape; and the one side of the second source electrode and the one side of the second drain electrode have a circular arc shape.
9 . The display element drive circuit according to claim 7 , wherein:
the second gate electrode has a rectangular planar shape; and at least a portion of the one side of the second source electrode and at least a portion of the one side of the second drain electrode have a linear shape.
10 . The display element drive circuit according to claim 1 , wherein:
the driving current control circuit comprises a drive transistor; the drive transistor comprises a third gate electrode, a third source electrode, a third drain electrode, a fifth parasitic capacitance formed between (i) one of the third source electrode and the third drain electrode and (ii) the third gate electrode, and a sixth parasitic capacitance formed between (i) the other of the third source electrode and the third drain electrode (ii) and the third gate electrode; said other of the second source electrode and the second drain electrode of the control transistor is connected to the third gate electrode; the power supply voltage is applied to said one of the third source electrode and the third drain electrode; said other of the third source electrode and the third drain electrode is connected to the display element; and the fifth parasitic capacitance and the sixth parasitic capacitance have capacitance values that are different from each other.
11 . The display element drive circuit according to claim 10 , wherein the capacitance value of the fifth parasitic capacitance is larger than the capacitance value of the sixth parasitic capacitance.
12 . The display element drive circuit according to claim 10 , wherein the capacitance value of the fifth parasitic capacitance is smaller than the capacitance value of the sixth parasitic capacitance.
13 . The display element drive circuit according to claim 10 , further comprising an electric charge holding circuit which holds electric charges based on the gradation signal as a voltage component;
wherein the driving current control circuit generates the driving current based on the voltage component held by the electric charge holding circuit; and wherein the electric charge holding circuit comprises a capacitance element connected between the third gate electrode of the drive transistor, and one of the third source electrode and the third drain electrode.
14 . The display element drive circuit according to claim 1 , wherein the display element includes an organic electroluminescent element.
15 . A display apparatus which displays image information, comprising at least a display panel having a plurality of scanning lines and a plurality of signal lines arranged to be orthogonal to each other, and a pixel arranged in a vicinity of each of respective intersections of the scanning lines and signal lines, wherein:
each of the display pixels comprises a current control type display element and a display element drive circuit which controls a light emitting operation of the display element; the display element drive circuit comprises at least (i) a driving current control circuit which has a gradation signal corresponding to display data supplied thereto, generates a driving current based on the gradation signal, and supplies the generated driving current to the display element, and (ii) a write control circuit which has a selection signal applied thereto and supplies the gradation signal to the driving current control circuit; the write control circuit comprises a write transistor and a control transistor; the write transistor comprises a first gate electrode, a first source electrode, a first drain electrode, a first parasitic capacitance formed between (i) one of the first source electrode and the first drain electrode and (ii) the first gate electrode, and a second parasitic capacitance formed between (i) the other of the first source electrode and the first drain electrode and (ii) the first gate electrode; the selection signal is applied to the first gate electrode; said one of the first source electrode and the first drain electrode is connected to the signal line; said other of the first source electrode and the first drain electrode is connected to the driving current control circuit; a capacitance value of the first parasitic capacitance is smaller than a capacitance value of the second parasitic capacitance; the control transistor comprises a second gate electrode, a second source electrode, a second drain electrode, a third parasitic capacitance formed between (i) one of the second source electrode and the second drain electrode and (ii) the second gate electrode, and a fourth parasitic capacitance formed between (i) the other of the second source electrode and the second drain electrode and (ii) the second gate electrode; the selection signal is applied to the second gate electrode; a predetermined power supply voltage is applied to said one of the second source electrode and the second drain electrode; said other of the second source electrode and the second drain electrode is connected to the driving current control circuit; and the third parasitic capacitance and the fourth parasitic capacitance have capacitance values that are different from each other.
16 . The display apparatus according to claim 15 , wherein the capacitance value of the third parasitic capacitance is larger than the capacitance value of the fourth parasitic capacitance.
17 . The display apparatus according to claim 15 , wherein the capacitance value of the third parasitic capacitance is smaller than the capacitance value of the fourth parasitic capacitance.
18 . The display apparatus according to claim 15 , wherein:
the driving current control circuit comprises a drive transistor; the drive transistor comprises a third gate electrode, a third source electrode, a third drain electrode, a fifth parasitic capacitance formed between (i) one of the third source electrode and the third drain electrode and (ii) the third gate electrode, and a sixth parasitic capacitance formed between (i) the other of the third source electrode and the third drain electrode and (ii) the third gate electrode; said other of the second source electrode and the second drain electrode of the control transistor is connected to the third gate electrode; the power supply voltage is applied to said one of the third source electrode and the third drain electrode; said other of the third source electrode and the third drain electrode is connected to the display element; and the fifth parasitic capacitance and the sixth parasitic capacitance have capacitance values that are different from each other.
19 . The display apparatus according to claim 18 , wherein the capacitance value of the fifth parasitic capacitance is larger than the capacitance value of the sixth parasitic capacitance.
20 . The display apparatus according to claim 18 , wherein the capacitance value of the fifth parasitic capacitance is smaller than the capacitance value of the sixth parasitic capacitance.
21 . The display apparatus according to claim 18 , wherein:
the display element drive circuit comprises an electric charge holding circuit which holds electric charges based on the gradation signal as a voltage component; the driving current control circuit generates the driving current based on the voltage component held by the electric charge holding circuit; and the electric charge holding circuit comprises a capacitance element connected between the third gate electrode of the drive transistor, and one of the third source electrode and the third drain electrode.Join the waitlist — get patent alerts
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