Nmos transistor with enhanced stress gate

Abstract

A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.

1 . An n-channel metal oxide semiconductor (NMOS) transistor, comprising an NMOS gate stack, further comprising:
 a n-type polysilicon layer formed on a top surface of a first gate dielectric layer;   a compressively stressed metal layer formed on a top surface of said n-type polysilicon layer; and   a p-type polysilicon layer formed on a top surface of said compressively stressed metal layer.   
     
     
         2 . The NMOS transistor of  claim 1 , in which said compressively stressed metal layer is comprised of a material selected from the group consisting of TiN, TaN, W and Mo. 
     
     
         3 . The NMOS transistor of  claim 1 , in which said compressively stressed metal layer is between 10 and 30 nanometers thick. 
     
     
         4 . The NMOS transistor of  claim 1 , in which said n-type polysilicon layer is between 2 and 20 nanometers thick. 
     
     
         5 . A complementary metal oxide semiconductor (CMOS) integrated circuit (IC), comprising:
 an NMOS transistor, further comprising an NMOS gate stack, further comprising:
 a n-type polysilicon layer formed on a top surface of a first gate dielectric layer; 
 a compressively stressed metal layer formed on a top surface of said n-type polysilicon layer; and 
 a p-type polysilicon layer formed on a top surface of said compressively stressed metal layer; and 
   a p-channel metal oxide semiconductor (PMOS) transistor, further comprising a PMOS gate stack further comprised of a second p-type polysilicon layer formed on a top surface of a second gate dielectric layer.   
     
     
         6 . The CMOS IC of  claim 5 , in which said compressively stressed metal layer is comprised of a material selected from the group consisting of TiN, TaN, W and Mo. 
     
     
         7 . The CMOS IC of  claim 5 , in which said compressively stressed metal layer is between 10 and 30 nanometers thick. 
     
     
         8 . The CMOS IC of  claim 5 , in which said n-type polysilicon layer is between 2 and 20 nanometers thick. 
     
     
         9 . The CMOS IC of  claim 5 , in which a difference in height between said NMOS gate stack and said PMOS gate stack is less than 10 nanometers. 
     
     
         10 . A method of forming a CMOS IC, comprising the steps of:
 forming a first polysilicon layer on a top surface of a first gate dielectric layer in an NMOS area and a top surface of a second gate dielectric layer in a PMOS area;   forming a compressively stressed metal layer on a top surface of said first polysilicon layer;   forming an NMOS stress layer photoresist pattern on a top surface of said compressively stressed metal layer in said NMOS area;   removing said compressively stressed metal layer from areas exposed by said NMOS stress layer photoresist pattern;   removing a portion of said first polysilicon layer from areas exposed by said NMOS stress layer photoresist pattern;   forming a second polysilicon layer on a top surface of said compressively stressed metal layer and a top surface of said first polysilicon layer;   forming a gate photoresist pattern on a top surface of said second polysilicon layer in said NMOS area over said compressively stressed metal layer and in said PMOS area;   removing said second polysilicon layer, said compressively stressed metal layer, and said first polysilicon layer from areas exposed by said gate photoresist pattern.   
     
     
         11 . The method of  claim 10 , in which said compressively stressed metal layer is comprised of a material selected from the group consisting of TiN, TaN, W and Mo. 
     
     
         12 . The method of  claim 10 , in which said compressively stressed metal layer is between 10 and 30 nanometers thick. 
     
     
         13 . The method of  claim 10 , in which said step of forming a second p-type polysilicon layer further comprises the step of performing a polysilicon chemical mechanical polish (CMP) operation in such a manner as to reduce a difference in height in said top surface of said second p-type polysilicon layer in said NMOS area and said PMOS area to less than 10 nanometers. 
     
     
         14 . The method of  claim 10 :
 in which said step of forming said first polysilicon layer further comprises the steps of:
 forming a first sublayer of undoped polysilicon on said top surface of said first gate dielectric layer in said NMOS area and said top surface of said second gate dielectric layer in said PMOS area; and 
 forming a second sublayer of n-type polysilicon on a top surface of said first sublayer of undoped polysilicon; and 
   in which said step of removing said compressively stressed metal layer and a portion of said first polysilicon layer from areas exposed by said NMOS stress layer photoresist pattern further comprises the steps of:
 removing said second sublayer of n-type polysilicon from areas exposed by said NMOS stress layer photoresist pattern; and 
 removing a portion of said first sublayer of undoped polysilicon from areas exposed by said NMOS stress layer photoresist pattern; and 
   further comprising the steps of:
 performing an n-type source/drain (NSD) anneal operation which causes n-type dopants in said second sublayer of n-type polysilicon to diffuse into said first sublayer of undoped polysilicon in said NMOS area; and 
 performing a p-type source/drain (PSD) anneal operation which causes p-type dopants in said second polysilicon layer to diffuse into said first sublayer of undoped polysilicon in said PMOS area. 
   
     
     
         15 . The method of  claim 10 , in which said first polysilicon layer is n-type. 
     
     
         16 . The method of  claim 10 , in which said second polysilicon layer is p-type. 
     
     
         17 . The method of  claim 10 , in which said second polysilicon layer is undoped.