Logical separation and accessing of descriptor memories

Abstract

A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the number of distinct memory portions. The packet header processing unit is configured to retrieve the different types of descriptor information from the number of distinct memory portions and to generate header information from the different types of descriptor information.

1 - 27 . (canceled) 
     
     
         28 . A device comprising:
 a plurality of data unit processing components, each of the plurality of data unit processing components, including:   a higher layer execution unit to:
 receive header information, where the header information includes template data and tag descriptor data, and 
 process the header information to obtain higher layer header data, the higher layer execution unit performing the processing of the received header information in parallel with processing of the header information by a lower layer execution unit associated with the one of the plurality of data unit processing components. 
   
     
     
         29 . The device of  claim 28 , where the header information further includes header data associated with a previously processed data unit 
     
     
         30 . The device of  claim 28 , further comprising:
 a plurality of mailbox registers to:   store information to allow the higher layer execution unit, of the one of the plurality of data unit processing components, to share data with the lower layer execution unit, associated with the one of the plurality of data unit processing components.   
     
     
         31 . The device of  claim 30 , where at least one mailbox register, of the plurality of mailbox registers, accepts data from the higher layer execution unit and does not accept data from the lower layer execution unit. 
     
     
         32 . The device of  claim 30 , where at least one mailbox register, of the plurality of mailbox registers, includes a validity bit that indicates whether the one mailbox register is ready to be written or read. 
     
     
         33 . The device of  claim 28 , further comprising:
 a build component to:
 receive the higher layer header data from the higher layer execution unit, and 
 form a header based on the higher layer header data and the lower layer header data received from the lower layer execution unit. 
   
     
     
         34 . The device of  claim 28 , where a data unit processing component, of the plurality of data unit processing components, loads information relating to a first header simultaneously with acquiring information relating to a second header. 
     
     
         35 . The device of  claim 28 , where the higher layer execution unit includes a plurality of execution sections, including:
 a first execution section, of the plurality of execution sections, to process the header information, and   a second execution section, of the plurality of execution sections, to compute a checksum.   
     
     
         36 . The device of  claim 28  further comprising:
 a dispatch component to:
 receive the header information associated with a data unit; 
 parse the received header information, and 
 to direct the parsed header information to two or more of the plurality of data unit processing components. 
 
 
     
     
         37 . A device comprising:
 input unit to:
 receive a data unit, and 
 determine header information associated with the data unit, where the header information includes template data and tag descriptor data; 
   a higher layer execution unit to:
 receive the header information, and 
 generate higher layer header data based on the header information, the higher layer execution unit generating the higher layer header data in parallel with generation of lower layer header data, associated with the header information, by an associated lower layer execution unit. 
   
     
     
         38 . The device of  claim 37 , further comprising:
 a dispatch component to:
 parse the header information to create parsed header information portions, and 
 direct one of the parsed header information portions to the higher layer execution unit. 
   
     
     
         39 . The device of  claim 37 , further comprising:
 at least one mailbox register to store information, the at least one mailbox register allowing the higher layer execution unit to share data with the lower layer execution unit.   
     
     
         40 . The device of  claim 39 , where the at least one mailbox register includes a first mailbox register and a second mailbox register, where the first mailbox register cannot be written to by the higher layer execution unit, and where the second mailbox register cannot be written to by the lower layer execution unit. 
     
     
         41 . The device of  claim 39 , where the at least one mailbox register includes a validity bit that indicates whether data associated with the at least one mailbox register is ready to be written or read. 
     
     
         42 . The device of  claim 37 , further comprising:
 a build component to combine the higher layer header data and the lower layer header data to form a header.   
     
     
         43 . The device of  claim 37 , where the higher layer execution unit is further to compute a checksum for the received header information. 
     
     
         44 . A method implemented in a device comprising a plurality of data unit processing components, the method comprising:
 receiving, at a higher layer execution unit in one of the a plurality of data unit processing components, header information including at least one of template data, tag descriptor data, or higher layer descriptor data;   generating, at the higher layer execution unit, higher layer header data based on the header information, where generating the higher layer header data occurring in parallel with generating, by one of the plurality of data unit processing components, lower layer header data associated with the header information; and   forming, based on the higher layer header data and the lower layer header data, a header.   
     
     
         45 . The method of  claim 44 , further comprising:
 transferring data to and from the higher layer execution unit using a first mailbox register.   
     
     
         46 . The method of  claim 44 , further comprising:
 transferring data to and from the lower layer execution unit using a second, different mailbox register that cannot be accessed by the higher layer execution unit.   
     
     
         47 . The method of  claim 44 , further comprising,
 computing a checksum for the header information, and   verifying the header information based on the checksum.