Vertical Non-Volatile Switch with Punchthrough Access and Method of Fabrication Therefor

Abstract

A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.

1 . A memory cell comprising a vertical stack of semiconductor layers and comprising a source, a drain, and a well without an associated gate structure, wherein application of a drain-source bias voltage generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain. 
     
     
         2 . The memory cell of  claim 1 , in combination with a resistive sense element (RSE), wherein said flow of current programs the RSE to a selected resistive state. 
     
     
         3 . The memory cell of  claim 1 , wherein the vertical stack of semiconductor layers is bidirectional. 
     
     
         4 . The memory cell of  claim 1 , wherein the vertical stack of semiconductor layers is a silicon compound. 
     
     
         5 . The memory cell of  claim 1 , wherein the source, drain, and well are doped to form an N-P-N mode. 
     
     
         6 . The memory cell of  claim 1 , wherein the source, drain, and well are doped to form an P-N-P mode. 
     
     
         7 . The memory cell of  claim 1 , wherein punchthrough mechanism extends adjacent a MOSFET channel in said well. 
     
     
         8 . The memory cell of  claim 1 , wherein the vertical stack of semiconductor layers has an insulating material on at least one sidewall. 
     
     
         9 . The memory cell of  claim 2 , wherein the RSE is connected vertically adjacent to the vertical stack of semiconductor layers. 
     
     
         10 . The memory cell of  claim 1 , wherein the punchthrough mechanism is generated with bidirectional voltage. 
     
     
         11 . The memory cell of  claim 1 , wherein the vertical stack of semiconductor layers is a bipolar and bidirectional switch in a cross-point array of memory. 
     
     
         12 . A method comprising:
 providing a memory cell comprising a resistive sense element (RSE) and a vertically stacked switching device comprising a source region, a drain region and a well region therebetween without an associated gate structure; and   using a punchthrough mechanism of the switching device to conduct current from the drain to the source.   
     
     
         13 . The method of  claim 12 , wherein a plurality of memory cells are each connected between one of a plurality of bit lines and one of a plurality of source lines in a cross-point array of memory. 
     
     
         14 . The method of  claim 13 , wherein a selected memory cell is connected between a first bit line and a first source line. 
     
     
         15 . The method of  claim 14 , wherein the first bit line is set to a high voltage and the first source line is set to a low voltage while the remaining plurality of bit lines and source lines are each set to a half voltage to prevent leak current from reaching the selected memory cell. 
     
     
         16 . The method of  claim 12 , wherein the source and drain of the vertically stacked switching device of the memory cell are biased with a threshold voltage to conduct current through the punchthrough mechanism. 
     
     
         17 . The method of  claim 16 , wherein a read current is subsequently passed through the RSE to read a programmed resistive state of the RSE. 
     
     
         18 . The method of  claim 16 , wherein a write current is subsequently passed through the RSE to program a resistive state of the RSE. 
     
     
         19 . A data storage device comprising a plurality of memory cells each connected between and controlled by one of a plurality of first and second control lines, each memory cell comprising a resistive sense element (RSE) connected in series with a vertical stack of semiconductor layers and comprising a source, a drain, and a well without an associated gate structure, wherein application of a drain-source bias voltage generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain to the RSE. 
     
     
         20 . The data storage device of  claim 19 , wherein a selected memory cell coupled between a selected first and second control line, the first selected control line charged to a first read voltage, the second selected control line charged to a second read voltage, and the memory cell is read after each non-selected first and second control line is precharged to a desired voltage that is between the first and second read voltages.