Charge pump circuit

Abstract

Each of a plurality of pump stages has an input node and an output node and performs a charge pump operation in response to any one of the first and second clock signals. The plurality of pump stages include a first pump stage, in which a charge transfer transistor is connected between the input node and the output node. One end of a pump capacitor is connected to the output node, and the other end is supplied with one of the first and second clock signals corresponding to the first pump stage. A connection switcher connects to the gate of the charge transfer transistor any one of the output node of a pump stage which is supplied with one of the clock signals corresponding to the first pump stage and the input node of a pump stage which is supplied with the other clock signal not corresponding to the first pump stage and which is included in a pump stage row not including the first pump stage.

1 - 10 . (canceled) 
     
     
         11 . A charge pump circuit which performs a charge pump operation in response to complementary first and second clock signals to generate a pumped voltage, comprising:
 a plurality of pump stage rows, each of which repeats a charge pump operation in response to the first and second clock signals;   a plurality of anti-backflow circuits respectively corresponding to the plurality of pump stage rows; and   an output terminal for outputting the pumped voltage,   wherein each of the plurality of anti-backflow circuits has an input node connected to the pump stage row, an output node connected to the output terminal, and an intermediate node at which a voltage is pumped in response to any one of the first and second clock signals, and   the plurality of anti-backflow circuits includes a first anti-backflow circuit, the first anti-backflow circuit including
 a charge transfer transistor connected between the input node and the output node, 
 a pump capacitor, one end of which is connected to the intermediate node, and the other end receiving one of the first and second clock signals corresponding to the first anti-backflow circuit, and 
 a connection switcher for connecting to a gate of the charge transfer transistor any one of an intermediate node of an anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit and an input node of an anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit. 
   
     
     
         12 . The charge pump circuit of  claim 11 , wherein:
 if an absolute value of a voltage at an input node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit is greater than or equal to an absolute value of a voltage at the input node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit, the connection switcher connects to the gate of the charge transfer transistor the intermediate node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit; and   if the absolute value of the voltage at the input node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit is smaller than the absolute value of the voltage at the input node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit, the connection switcher connects to the gate of the charge transfer transistor the input node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit.   
     
     
         13 . A charge pump circuit which performs a charge pump operation in response to complementary first and second clock signals to generate a pumped voltage, comprising:
 a plurality of pump stage rows, each of which repeats a charge pump operation in response to the first and second clock signals;   a plurality of anti-backflow circuits respectively corresponding to the plurality of pump stage rows: and   an output terminal for outputting the pumped voltage,   wherein each of the plurality of anti-backflow circuits has an input node connected to the pump stage row, an output node connected to the output terminal, and an intermediate node at which a voltage is pumped in response to any one of the first and second clock signals, and   the plurality of anti-backflow circuits includes a first anti-backflow circuit, the first anti-backflow circuit including
 a charge transfer transistor connected between the input node and the output node, 
 a pump capacitor, one end of which is connected to the intermediate node, and the other end receiving one of the first and second clock signals corresponding to the first anti-backflow circuit, and 
 a connection switcher for connecting to a gate of the charge transfer transistor any one of an input node of an anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit and an intermediate node of an anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit. 
   
     
     
         14 . The charge pump circuit of  claim 13 , wherein the connection switcher includes:
 an off-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the input node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit, and a gate connected to an input node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit; and   an on-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the intermediate node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit, and a gate connected to an intermediate node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit.   
     
     
         15 . The charge pump circuit of  claim 13 , wherein the connection switcher includes:
 an off-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the input node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit, and a gate connected to the output terminal; and   an on-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the intermediate node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit, and a gate connected to the output terminal.   
     
     
         16 . The charge pump circuit of  claim 13 , further comprising an analog comparator circuit for comparing a voltage at an intermediate node of an anti-backflow circuit corresponding to the first clock signal and a voltage at an intermediate node of an anti-backflow circuit corresponding to the second clock signal to select any one of the intermediate nodes of these two anti-backflow circuits according to a result of the comparison,
 wherein the connection switcher includes
 an off-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the input node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit, and a gate connected to the intermediate node selected by the analog comparator circuit, and 
 an on-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the intermediate node of the anti-backflow circuit which is supplied with the other clock signal corresponding to the first anti-backflow circuit, and a gate connected to the intermediate node selected by the analog comparator circuit. 
   
     
     
         17 . The charge pump circuit of  claim 13 , wherein:
 the first anti-backflow circuit further includes a subsidiary charge transfer transistor located between the input node and the output node and connected in series with the charge transfer transistor, the subsidiary charge transfer transistor having a gate connected to the intermediate node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit;   the connection switcher includes
 an off-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the input node of the anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit, and a gate connected to a gate control node, and 
 an on-switch transistor that has a drain connected to the gate of the charge transfer transistor, a source connected to the intermediate node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit, and a gate connected to the gate control node; and 
   a connection node of the charge transfer transistor and the subsidiary charge transfer transistor is connected to the gate control node.   
     
     
         18 . A charge pump circuit which performs a charge pump operation in response to complementary first and second clock signals to generate a pumped voltage, comprising:
 a plurality of pump stage rows, each of which repeats a charge pump operation in response to the first and second clock signals;   a plurality of anti-backflow circuits respectively corresponding to the plurality of pump stage rows; and   an output terminal for outputting the pumped voltage,   wherein each of the plurality of anti-backflow circuits has an input node connected to the pump stage row and an intermediate node at which a voltage is pumped in response to any one of the first and second clock signals,   the plurality of anti-backflow circuits includes a first anti-backflow circuit, the first anti-backflow circuit including
 a charge transfer transistor connected between the input node and the intermediate node, 
 a pump capacitor, one end of which is connected to the intermediate node, and the other end receiving one of the first and second clock signals corresponding to the first anti-backflow circuit, 
 a connection switcher for connecting to a gate of the charge transfer transistor any one of an input node of an anti-backflow circuit which is supplied with the clock signal corresponding to the first anti-backflow circuit and the intermediate node of an anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit, and 
 a subsidiary charge transfer transistor located between the input node and the intermediate node and connected in series with the charge transfer transistor, the subsidiary charge transfer transistor having a gate connected to an intermediate node of the anti-backflow circuit which is supplied with the other clock signal not corresponding to the first anti-backflow circuit, and 
   a connection node of the charge transfer transistor and the subsidiary charge transfer transistor is connected to the output terminal.   
     
     
         19 . The charge pump circuit of  claim 13 , wherein the first anti-backflow circuit further includes a diode-connected transistor connected between the input node and the intermediate node. 
     
     
         20 . The charge pump circuit of  claim 13 , wherein the first anti-backflow circuit further includes a diode-connected transistor connected between a voltage node which receives a supply voltage or ground voltage and the intermediate node. 
     
     
         21 . The charge pump circuit of  claim 18 , wherein the first anti-backflow circuit further includes a diode-connected transistor connected between the intermediate node and the connection node of the charge transfer transistor and the subsidiary charge transfer transistor.