Circuit for classifying signals

Abstract

A circuit for classification of analog input signals, comprising an analog memory component, such as a floating gate, used to store a threshold value; a threshold detection module used to determine whether the analog input signal exceeds the threshold value; a time delay module used to delay a processing of the analog signal; a time-amplitude window calculation module used to determine whether an amplitude of the analog input signal is between a lower limit and an upper limit of an amplitude window; and an output module indicating whether the amplitude of the analog signal is between the lower and the upper limit, wherein the indication is used to determine whether the analog input signal belongs to one of a plurality of analog signal classes. The classification is implemented in the analog domain, eliminating the need for sampling and digitizing the analog signal, consequently minimizing circuit area and power.

1 . A circuit for classification of analog input signals, the circuit comprising:
 a first analog memory component operative to store a threshold value;   a threshold detection module operative to determine whether the analog input signal exceeds the threshold value;   a time delay module operative to delay a processing of the analog input signal by an amount equal to a window time delay;   an amplitude window calculation module operative to determine, after a lapse of the window time delay, whether an amplitude of the analog input signal is between a lower limit and an upper limit of an amplitude window; and   an output module providing an indication of whether the amplitude of the analog input signal is between the lower limit and the upper limit of the amplitude window, wherein the indication is used to determine whether the analog input signal belongs to at least one of a plurality of pre-determined classes of analog signals.   
     
     
         2 . The circuit of  claim 1 , wherein the first analog memory component comprises a floating gate of a transistor. 
     
     
         3 . The circuit of  claim 1 , wherein the analog signal amplitude window determination module comprises an electronic operational amplifier having an inverting and a non-inverting input terminal. 
     
     
         4 . The circuit of  claim 1 , wherein the time delay module delays the processing of the analog input signal by disabling the analog signal amplitude window determination module for a period of time equal to the predetermined time delay. 
     
     
         5 . The circuit of  claim 1 , wherein the threshold value comprises an electrical charge corresponding to a first numerical value of the analog input signal. 
     
     
         6 . The circuit of  claim 1 , wherein the lower limit and the upper limit of the amplitude window comprise electrical charges stored in a second and a third analog memory component, respectively. 
     
     
         7 . The circuit of  claim 1 , wherein the indication provided by the output module comprises at least one digital signal indicating whether the amplitude of the analog input signal is greater than the lower limit and less than the upper limit. 
     
     
         8 . The circuit of  claim 7 , wherein the output module comprises a logic circuit for logically combining results of the determination of the amplitude of the analog input signal being greater than the lower limit and less than the upper limit and outputting the at least one digital signal. 
     
     
         9 . The circuit of  claim 1 , wherein the time delay module comprises an analog delay circuit. 
     
     
         10 . The circuit of  claim 9 , wherein the analog delay circuit comprises a first delay analog memory component, a second delay analog memory component, a capacitor, and a delay operational amplifier. 
     
     
         11 . The circuit of  claim 10 , wherein the first delay analog memory component is used to store an electrical charge corresponding to a rate of electrical charge-up of the capacitor. 
     
     
         12 . The circuit of  claim 11 , wherein the capacitor provides an electrical charge-up delay corresponding to the window time delay. 
     
     
         13 . The circuit of  claim 10 , wherein the second delay analog memory component is used to set the maximum electrical charge held by the capacitor. 
     
     
         14 . The circuit of  claim 1 , wherein the time delay module comprises a digital delay circuit. 
     
     
         15 . The circuit of  claim 14 , wherein the digital delay circuit comprises a counter component, a compare register component operable to store a digital value corresponding to a time delay value, and a digital comparator component operable to compare an output of the counter component and the digital value corresponding to the time delay value. 
     
     
         16 . An array of analog circuits for detection of patterns of analog input signals, the array of analog circuits comprising:
 a plurality of input ports operative to receive a plurality of analog input signals;   a plurality of circuits, corresponding to the plurality of the input ports, each operative to receive one of the plurality of the analog input signals, each circuit comprising:
 a first analog memory component operative to store a threshold value; 
 a threshold detection module operative to determine whether the analog input signal exceeds the threshold value; 
 a time delay module operative to delay a processing of the one of the analog input signals by an amount equal to a corresponding window time delay; 
 an amplitude window calculation module operative to determine, after a lapse of the corresponding window time delay, whether an amplitude of the one of the analog input signals is between a corresponding lower limit and a corresponding upper limit of a corresponding amplitude window; and 
 an output module providing an indication of whether the amplitude of the one of the analog input signals is between the corresponding lower and the corresponding upper limit of the corresponding amplitude window, wherein the indication is used to determine whether the one of the analog input signals belongs to at least one of a plurality of pre-determined classes of analog signals; and 
   an array control module operative to select one of the plurality of the circuits.   
     
     
         17 . The array of analog circuits of  claim 16 , wherein the plurality of the analog input signals are pre-amplified before being received by the plurality of the input ports. 
     
     
         18 . The array of circuits of  claim 16 , wherein the plurality of the circuits are connected to at least an address bus for selecting one of the plurality of the circuits, an analog bus for delivering the plurality of the analog input signals to a signal processor, and a spike bus for delivering the indications provided by each of the output modules of the plurality of the circuits to the signal processor. 
     
     
         19 . The array of circuits of  claim 18 , wherein the array control module comprises an address decoder for selecting one of the plurality of the circuits using at least one of the address bus, the analog bus, and the spike bus. 
     
     
         20 . A device for detection of patterns of analog input signals, the device comprising:
 an array of circuits;   a plurality of input ports operative to receive a plurality of analog input signals;   a plurality of circuits, corresponding to the plurality of the input ports, each operative to receive one of the plurality of the analog input signals, each circuit comprising:
 a first analog memory component operative to store a threshold value; 
 a threshold detection module operative to determine whether the analog input signal exceeds the threshold value; 
 a time delay module operative to delay a processing of the one of the analog input signals by an amount equal to a corresponding window time delay; 
 an amplitude window calculation module operative to determine, after a lapse of the corresponding window time delay, whether an amplitude of the one of the analog input signals is between a corresponding lower limit and a corresponding upper limit of a corresponding amplitude window; and 
 an output module providing an indication of whether the amplitude of the one of the analog input signals is between the corresponding lower and the corresponding upper limit of the corresponding amplitude window, wherein the indication is used to determine whether the one of the analog input signals belongs to at least one of a plurality of pre-determined classes of analog signals; 
   an array control module operative to select one of the plurality of the circuits; and   a communication interface module operative to transfer information to/from the analog device.   
     
     
         21 . The analog device of  claim 20  further comprising a power source to power the analog circuits. 
     
     
         22 . The analog device of  claim 20 , wherein an external power source is used to power the analog circuits. 
     
     
         23 . The analog device of  claim 20 , wherein the communication interface module comprises a serial interface. 
     
     
         24 . The analog device of  claim 20 , wherein the communication interface module comprises a wireless communication interface.