Superconducting circuit for high-speed lookup table

Abstract

A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

1 . A pipelined multi-bit processor, comprising:
 an input port configured to receive a multibit digital value;   a processing network comprising a pipeline of successive processing stages employing superconducting elements, wherein the digital value is transformed in dependence on pipeline logic and passed to succeeding stages of the pipeline in dependence on a clock cycle; and   at least one output port, configured to present an output in dependence on the received digital value, the clock cycle, the pipeline logic and a respective stage of the pipeline with which the output port is associated.   
     
     
         2 . The pipelined multi-bit processor according to  claim 1 , wherein the pipeline logic implements a code matching network, configured to generate a plurality of output signals corresponding to the multibit digital value, further comprising a plurality of code-matching cells organized into rows and columns, each cell comprising a clocked rapid-single-flux-quantum device, having a column associated with each bit of the multibit digital value, and a row associated a respective output port, wherein the pipeline logic is configured to provide a variable time delay between a receipt of the multibit digital value at the input port, and presentation of the output at the output port, of an integral number of clock cycles, a value of the integral number varying in dependence on the multibit digital value. 
     
     
         3 . The pipelined multi-bit processor according to  claim 2 , further comprising a pipelined memory array, configured to receive the output from the output port, and to produce an memory output representing a memory contents of at least one memory cell at an address of the pipelined memory array defined by the multibit digital input, the memory output having a total time delay between receipt of the multibit digital value and production of the memory output of an integral number of clock cycles that is independent of the multibit digital value. 
     
     
         4 . The pipelined multi-bit processor according to  claim 2 , wherein each code-matching cell comprises a clocked data flip-flop having a regular output and complementary output, wherein either the regular output or the complementary output of the data flip-flop is connected to a respective network output line, depending on a bit value of a respective bit of the multibit digital value. 
     
     
         5 . The pipelined multi-bit processor according to  claim 2 , wherein each code-matching cell comprises either a clocked data flip-flop or a clocked inverter, whereby the output of the code-matching cell is connected to the input of the succeeding row, as well as to a respective network output line. 
     
     
         6 . The pipelined multi-bit processor according to  claim 1 , wherein the transformed multibit digital value is passed to succeeding stages. 
     
     
         7 . The pipelined multi-bit processor according to  claim 1 , wherein the multibit digital value is passed to succeeding stages in a non-transformed state. 
     
     
         8 . A pipelined processing method, comprising:
 receiving a multibit digital value;   processing the received multibit digital value with a processing network comprising a pipeline of successive processing stages employing superconducting elements, wherein the digital value is transformed in dependence on pipeline logic and passed to succeeding stages of the pipeline in dependence on a clock cycle; and   presenting an output in dependence on the received digital value, the clock cycle, the pipeline logic and a respective stage of the pipeline with which the output port is associated,   wherein the pipeline logic implements a code matching network, generating a plurality of output signals corresponding to the multibit digital value, further comprising a plurality of code-matching cells organized into rows and columns, each cell comprising a clocked rapid-single-flux-quantum device, having a column associated with each bit of the multibit digital value, and a row associated a respective output port, wherein the pipeline logic provides a variable time delay between a receipt of the multibit digital value at the input port, and presentation of the output at the output port, of an integral number of clock cycles, a value of the integral number varying in dependence on the multibit digital value,   and the ouput port is received by a pipelined memory array, which produces an memory output representing a memory contents of at least one memory cell at an address of the pipelined memory array defined by the multibit digital input,   the memory output having a total time delay between receipt of the multibit digital value and production of the memory output of an integral number of clock cycles that is independent of the multibit digital value.   
     
     
         9 . The method according to  claim 8 , wherein each code-matching cell comprises a clocked data flip-flop having a regular output and complementary output, wherein either the regular output or the complementary output of the data flip-flop is connected to a respective network output line, depending on a bit value of a respective bit of the multibit digital value. 
     
     
         10 . The method according to  claim 8 , wherein each code-matching cell comprises either a clocked data flip-flop or a clocked inverter, whereby the output of the code-matching cell is connected to the input of the succeeding row, as well as to a respective network output line. 
     
     
         11 . The method according to  claim 8 , wherein the transformed multibit digital value is passed to succeeding stages. 
     
     
         12 . The method according to  claim 8 , wherein the multibit digital value is passed to succeeding stages in a non-transformed state. 
     
     
         13 . A pipelined multi-bit processor comprising a code matching network, configured to generate a plurality of output signals corresponding to a multibit digital input value received at an input port, comprising a plurality of code-matching cells organized into rows and columns, each cell comprising a clocked rapid-single-flux-quantum device, having a row associated with a respective multibit digital value, and columns of the row which together define an output value, configured to selectively provide a variable time delay of an integral number of clock cycles between a receipt of the multibit digital value at the input port, and presentation of the output at an output port, a value of the integral number selectively varying in dependence on the multibit digital value. 
     
     
         14 . The pipelined multi-bit processor according to  claim 13 , further comprising a pipelined memory array, configured to receive the output from the output, and to produce an memory output representing a memory contents of at least one memory cell corresponding to the output, the memory output having a total time delay between receipt of the multibit digital value and production of the memory output of an integral number of clock cycles that is independent of the multibit digital value. 
     
     
         15 . The pipelined multi-bit processor according to  claim 13 , wherein each code-matching cell comprises a clocked data flip-flop having a regular output and complementary output, wherein either the regular output or the complementary output of the data flip-flop is connected to a respective network output line, depending on a bit value of a respective bit of the multibit digital value. 
     
     
         16 . The pipelined multi-bit processor according to  claim 13 , wherein each code-matching cell comprises either a clocked data flip-flop or a clocked inverter, whereby the output of the code-matching cell is connected to the input of a succeeding row, as well as to a respective network output line.