Method for manufacturing a stacked semiconductor package, and stacked semiconductor package

Abstract

A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.

1 . A stacked semiconductor package, comprising:
 a substrate;   a plurality of semiconductor chips subsequently formed on the substrate and having respective insulating layers at sides thereof such that the insulating layers of the plurality of semiconductor chips are positioned at the same side as one another; and   a wiring formed over the insulating layers at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips is electrically connected with the substrate.   
     
     
         2 . The stacked semiconductor package as set forth in  claim 1 , wherein the insulating layers are formed at both sides of the corresponding semiconductor chips and the wiring conducts the electric connection for the plurality of semiconductor chips and the substrate via the insulating layers. 
     
     
         3 . The stacked semiconductor package as set forth in  claim 1 , wherein a thickness of the insulating layer at the side thereof is greater than a thickness of the insulating layer at a top thereof. 
     
     
         4 . The stacked semiconductor package as set forth in  claim 1 , wherein the insulating layer is elongated from a top of the semiconductor chip to a side thereof. 
     
     
         5 . The stacked semiconductor package as set forth in  claim 1 , wherein the semiconductor chip includes a tapered portion at the side thereof with the insulating layer.