US2011159644A1PendingUtilityA1

Semiconductor device and a method of manufacturing the same

Assignee: RENESAS ELECTRONICS CORPPriority: Jan 6, 2006Filed: Jan 6, 2011Published: Jun 30, 2011
Est. expiryJan 6, 2026(expired)· nominal 20-yr term from priority
H10W 74/00H10W 72/0198H10W 72/884H10W 72/547H10W 72/5449H10W 72/5473H10W 72/5522H10W 72/59H10W 72/5434H10W 72/5363H10W 72/536H10W 90/754H10W 90/752H10W 72/531H10W 72/07553H10W 72/932H10W 46/607H10W 46/101H10W 99/00H10W 72/075H10W 72/07533H10W 72/07521H10W 72/07504H10W 72/015H10W 72/07511H10W 72/07141H10W 90/734H10W 90/732H10W 90/00H10P 72/7418H10P 72/74H10W 90/28H10W 72/5525H10W 72/5445H10W 74/117H10W 74/111H10W 74/014H10W 70/65H10W 46/00
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Claims

Abstract

Wire connection failure in semiconductor device is prevented. A semiconductor device has a package substrate having, at the periphery of the main surface thereof, a plurality of bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the plurality of wires, and a plurality of solder bumps disposed on the back surface of the package substrate. The top of the loop of each of the wires is disposed outside the wire connecting portion so that the wire length wire can be increased in the connection between the bonding leads and the pads of the semiconductor chip. As a result, the wires have a stable loop shape and a wire connection failure can be prevented.

Claims

exact text as granted — not AI-modified
1 - 7 . (canceled) 
     
     
         8 . A method of manufacturing a semiconductor device, comprising the steps of:
 (a) providing a wiring substrate having a front surface, a back surface opposite to the front surface, and a bonding lead formed on the front surface;   (b) after the step (a), mounting a semiconductor chip on the front surface of the wiring substrate such that the bonding lead is exposed from the semiconductor chip in plan view;   (c) after the step (b), electrically connecting a first part of a wire with the bonding lead of the wiring substrate; and   (d) after the step (c), electrically connecting a second part of the wire with an electrode of the semiconductor chip,   wherein in the steps (c) and (d), the wire is formed by using a capillary,   wherein the capillary is moved to the electrode from a first portion side in a first direction, after the capillary is moved toward the first portion side from the bonding lead in the first direction,   wherein the first portion is located farther from the semiconductor chip than the first part of the wire in the first direction,   wherein the wire has a third part arranged between the first part and the second part, and   wherein after the step (d), the third part of the wire is located at the first portion.   
     
     
         9 . The method according to  claim 8 ,
 wherein after the step (d), a fourth part of the wire arranged between the second part and the third part is located at the first portion and is located farther from the front surface of the wiring substrate than the third part of the wire.   
     
     
         10 . The method according to  claim 8 ,
 wherein the bonding lead is arranged to be at a periphery of the front surface.   
     
     
         11 . The method according to  claim 8 ,
 wherein the wire is formed to have a loop shape.   
     
     
         12 . The method according to  claim 8 , further comprising:
 before the step (d), forming a bump on the electrode, and   wherein said electrically connecting of the step (d) is performed by contact bonding.   
     
     
         13 . The method according to  claim 12 ,
 wherein said forming a bump is performed before the step (c).   
     
     
         14 . The method according to  claim 8 ,
 wherein said electrically connecting of the step (d) is performed without using a bump.

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