Metal Oxide Semiconductor (MOS) Type Semiconductor Device And Manufacturing Method Thereof

Abstract

A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

1 .- 4 . (canceled) 
     
     
         5 . A semiconductor device having a metal oxide semiconductor (MOS) type transistor structure, comprising:
 an additional load capacitance that is formed at a part of the semiconductor device, which is vulnerable to soft errors;   wherein the semiconductor device having the MOS type transistor structure includes at least an n-type MOS transistor, and   the part that is vulnerable to soft errors is a drain of the n-type MOS type transistor.   
     
     
         6 . The semiconductor device according to  claim 5 , wherein the semiconductor device having the MOS type transistor structure is a static random access memory (SRAM) type memory cell having a flip-flop circuit that comprises a plurality of the n-type MOS transistors and a plurality of p-type MOS transistors. 
     
     
         7 .- 20 . (canceled) 
     
     
         21 . The semiconductor device according to  claim 5 , wherein the semiconductor device having the MOS type transistor structure further includes a p-type MOS transistor, and
 the part that is vulnerable to soft errors includes a drain of the p-type MOS transistor.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein the semiconductor device having the MOS type transistor structure is a static random access memory (SPAM) type memory cell having a flip-flop circuit that comprises a plurality of the n-type MOS transistors and a plurality of the p-type MOS transistors. 
     
     
         23 . The semiconductor device according to  claim 5 , wherein the additional load capacitance part of the semiconductor device is formed via an ordinary ion implantation as well as an additional ion implantation that is selectively performed in addition to ordinary ion implantation at a time of forming a well region in the MOS type transistor structure. 
     
     
         24 . The semiconductor device according to  claim 23 , wherein the semiconductor device having the MOS type transistor structure is a static random access memory (SRAM) type memory cell having a flip-flop circuit that comprises a plurality of the n-type MOS transistors and a plurality of p-type MOS transistors. 
     
     
         25 . The semiconductor device according to  claim 23 , wherein the semiconductor device having the MOS type transistor structure further includes a p-type MOS transistor, and
 the part that is vulnerable to soft errors includes a drain of the p-type MOS transistor.   
     
     
         26 . The semiconductor device according to  claim 25 , wherein the semiconductor device having the MOS type transistor structure is a static random access memory (SPAM) type memory cell having a flip-flop circuit that comprises a plurality of the n-type MOS transistors and a plurality of the p-type MOS transistors. 
     
     
         27 . The semiconductor device according to  claim 23  wherein a well region having a higher concentration than the other well region is formed at the part that is vulnerable to soft errors. 
     
     
         28 . The semiconductor device according to  claim 27 , wherein the semiconductor device having the MOS type transistor structure is a static random access memory (SRAM) type memory cell having a flip-flop circuit that comprises a plurality of the n-type MOS transistors and a plurality of p-type MOS transistors. 
     
     
         29 . The semiconductor device according to  claim 27 , wherein the semiconductor device having the MOS type transistor structure further includes a p-type MOS transistor, and
 the part that is vulnerable to soft errors includes a drain of the p-type MOS transistor.   
     
     
         30 . The semiconductor device according to  claim 29 , wherein the semiconductor device having the MOS type transistor structure is a static random access memory (SPAM) type memory cell having a flip-flop circuit that comprises a plurality of the n-type MOS transistors and a plurality of the p-type MOS transistors.