Semiconductor device

Abstract

A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor.

1 . A semiconductor device, comprising:
 a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon, wherein the first-type and the second-type are opposite conductivity types with respect to each other;   a first stress layer only disposed on the first-type MOS transistor; and   a second stress layer different from the first stress layer, only disposed on the core second-type MOS transistor;   wherein the I/O second-type MOS transistor is a type of I/O MOS transistor and without not only the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor.   
     
     
         2 . The semiconductor device of  claim 1 , wherein if the first-type MOS transistor is an N-channel MOS (NMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are P-channel MOS (PMOS) transistors, the first stress layer is a tensile stress layer and the second stress layer is a compressive stress layer. 
     
     
         3 . The semiconductor device of  claim 1 , wherein if the first-type MOS transistor is a P-channel MOS (PMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are N-channel MOS (NMOS) transistors, the first stress layer is a compressive stress layer and the second stress layer is a tensile stress layer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first stress layer is made of a material comprising silicon nitride. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the second stress layer is made of a material comprising silicon nitride. 
     
     
         6 . A semiconductor device, comprising:
 a substrate having a first-type MOS transistor, an input/output (I/O) MOS transistor of second-type, and a core MOS transistor of second-type formed thereon, wherein the first-type and the second-type are opposite conductivity types with respect to each other;   a first stress layer disposed on at least the first-type MOS transistor but not the core MOS transistor; and   a second stress layer different from the first stress layer, the second stress layer being disposed on the core MOS transistor but not the first-type MOS transistor, and further disposed on the I/O MOS transistor if the I/O MOS transistor is overlaid by the first stress layer, wherein one of the first stress layer and the second stress layer is a tensile layer and the other one of the first stress layer and the second stress layer is a compressive layer.   
     
     
         7 . A semiconductor device, comprising:
 a substrate having a first-type MOS transistor, an input/output (I/O) MOS transistor of second-type, and a core MOS transistor of second-type formed thereon;   a first stress layer disposed on the first-type MOS transistor and the I/O MOS transistor; and   a second stress layer different from the first stress layer, disposed on the core MOS transistor. wherein the first stress layer disposed on the I/O MOS transistor comprises a plurality of broken Si—H links and H+ are moving out of the first stress layer, upon the application of a negative bias on the substrate.   
     
     
         8 . The semiconductor device of  claim 7 , wherein each of the first stress layer and the second stress layer is one of a tensile stress layer and a compressive stress layer determined by conductivity types of the first-type and the second-type.