Dense arrays and charge storage devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

1 . A memory device, comprising:
 a substrate;   a vertical semiconductor channel located over the substrate;   first and second contacts contacting the vertical semiconductor channel;   a first charge storage region located adjacent to a first portion of the vertical semiconductor channel;   a first control gate located adjacent to the first charge storage region;   a second charge storage region located adjacent to a second portion of the vertical semiconductor channel above the first portion of the vertical semiconductor channel;   a second control gate located adjacent to the second charge storage region; and   a continuous tunneling dielectric located between a side of the vertical semiconductor channel and both the first and the second charge storage regions.   
     
     
         2 . The memory device of  claim 1 , wherein the vertical semiconductor channel comprises a silicon channel. 
     
     
         3 . The memory device of  claim 1 , wherein the first contact contacts a lower portion of the vertical semiconductor channel and the second contact contacts an upper portion of the vertical semiconductor channel. 
     
     
         4 . The memory device of  claim 3 , wherein the first and the second control gates are located above the first contact and below the second contact over the substrate. 
     
     
         5 . The memory device of  claim 1 , wherein the second control gate is located above the first control gate. 
     
     
         6 . The memory device of  claim 5 , further comprising an insulating layer which is located between the first and the second control gates and electrically isolates the first control gate from the second control gate. 
     
     
         7 . The memory device of  claim 1 , wherein:
 the first charge storage region comprises a first dielectric isolated floating gate located between the vertical semiconductor channel and the first control gate; and   and the second charge storage region comprises a second dielectric isolated floating gate located between the vertical semiconductor channel and the second control gate.   
     
     
         8 . The memory device of  claim 1 , wherein the first charge storage region and the second charge storage region comprise an ONO dielectric film or an insulating layer containing conductive nanocrystals. 
     
     
         9 . The memory device of  claim 1 , wherein the first charge storage region and the second charge storage region comprise a continuous dielectric film located between a side of the vertical semiconductor channel and both the first and the second control gates. 
     
     
         10 . The memory device of  claim 1 , wherein vertical semiconductor channel comprises a semiconductor pillar. 
     
     
         11 . The memory device of  claim 1 , wherein vertical semiconductor channel comprises a first semiconductor pillar and a second semiconductor pillar. 
     
     
         12 . The memory device of  claim 1 , wherein the device comprises a monolithic three dimensional array of charge storage devices comprising a plurality of device levels. 
     
     
         13 . A memory device, comprising:
 a substrate;   a vertical semiconductor channel located over the substrate;   first and second contacts contacting the vertical semiconductor channel;   a first charge storage region located adjacent to a first portion of the vertical semiconductor channel;   a first control gate located adjacent to the first charge storage region;   a second charge storage region located adjacent to a second portion of the vertical semiconductor channel above the first portion of the vertical semiconductor channel; and   a second control gate located adjacent to the second charge storage region;   wherein the first charge storage region and the second charge storage region comprise a continuous layer or film located between a side of the vertical semiconductor channel and both the first and the second control gates.   
     
     
         14 . The memory device of  claim 13 , wherein the vertical semiconductor channel comprises a silicon channel. 
     
     
         15 . The memory device of  claim 13 , wherein the first contact contacts a lower portion of the vertical semiconductor channel and the second contact contacts an upper portion of the vertical semiconductor channel. 
     
     
         16 . The memory device of  claim 15 , wherein the first and the second control gates are located above the first contact and below the second contact over the substrate. 
     
     
         17 . The memory device of  claim 13 , wherein the second control gate is located above the first control gate. 
     
     
         18 . The memory device of  claim 17 , further comprising an insulating layer which is located between the first and the second control gates and electrically isolates the first control gate from the second control gate. 
     
     
         19 . The memory device of  claim 13 , the first charge storage region and the second charge storage region comprise a continuous insulating layer or film. 
     
     
         20 . The memory device of  claim 13 , wherein the first charge storage region and the second charge storage region comprise an ONO dielectric film or an insulating layer containing conductive nanocrystals. 
     
     
         21 . The memory device of  claim 13 , further comprising a continuous tunneling dielectric located between a side of the vertical semiconductor channel and both the first and the second charge storage regions. 
     
     
         22 . The memory device of  claim 13 , wherein vertical semiconductor channel comprises a semiconductor pillar. 
     
     
         23 . The memory device of  claim 13 , wherein vertical semiconductor channel comprises a first semiconductor pillar and a second semiconductor pillar. 
     
     
         24 . The memory device of  claim 13 , wherein the device comprises a monolithic three dimensional array of charge storage devices comprising a plurality of device levels.