Optimizing pcb power and ground connections for lead free solder processes

Abstract

Apparatuses and methods that provide for enhanced connections between PTHs of multi-layer PCBs and electronic component leads, pins or the like. The apparatuses and methods improve the likelihood that the PTHs are completely filled with solder thereby advantageously allowing the PCBs to exhibit high mechanical and electrical reliability. Complete filling of PTHs is achieved by configuring the electrically conductive layers within the multi-layer PCB stack in a manner that reduces the heat sinking effects of the layers during the soldering process. In this regard, the PTHs may not directly contact all of the internal ground or power planes, so the heat sinking or heat transfer effects are reduced. This feature enables molten solder to substantially or completely fill an entire PTH before freezing.

1 . A method of attaching an electronic component to a multi-layer printed circuit board, the method comprising:
 providing a multi-layer printed circuit board that includes:
 a plurality of electrically conductive layers with dielectric material disposed between the electrically conductive layers, the plurality of electrically conductive layers including a first group of a planes and a second group of planes; 
 a first plated through-hole that extends through the multi-layer printed circuit board, the first plated through-hole including an electrically conductive lining that forms a barrel for receiving a first lead of the electronic component; and 
 a second plated through-hole that extends through the multi-layer printed circuit board, the second plated through-hole including an electrically conductive lining that forms a barrel for receiving a second lead of the electronic component; 
 wherein each of the first group of planes comprises an amount of an electrically conductive material, and wherein at least one of the first group of planes is electrically and mechanically connected to the electrically conductive lining of the first plated through-hole; and 
 wherein each of the second group of planes comprises an amount of an electrically conductive material, wherein at least one of the second group of planes is electrically and mechanically connected to the electrically conductive lining of the second plated through-hole, and wherein a ratio of the total amount of electrically conductive material of the at least one of the first group of planes that is electrically and mechanically connected to the electrically conductive lining of the first plated through-hole to the total amount of electrically conductive material of the at least one of the second group of planes that is electrically and mechanically connected to the electrically conductive lining of the second plated through-hole is substantially 1:1; 
   positioning the first lead of the electronic component within the first plated through-hole;   positioning the second lead of the electronic component within the second plated through-hole;   soldering the first lead to the electrically conductive lining of the first plated through-hole; and   soldering the second lead to the electrically conductive lining of the second plated through-hole.   
     
     
         2 . The method of  claim 1 , wherein the soldering the first lead step and soldering the second lead step respectively comprise:
 electrically coupling the first lead to the at least one of the first group of planes; and   electrically coupling the second lead to the at least one of the second group of planes.   
     
     
         3 . The method of  claim 1 , wherein the soldering the first lead step and the soldering the second lead step respectively comprise:
 filling a substantial entirety of the first plated through-hole with solder; and   filling a substantial entirety of the second plated through-hole with solder.   
     
     
         4 . The method of  claim 1 , wherein each of the soldering the first lead step and the soldering the second lead step comprises:
 performing a wave soldering process.   
     
     
         5 . The method of  claim 1  wherein the first group of planes comprises a set of ground planes and wherein the second group of planes comprises a set of power planes. 
     
     
         6 . The method of  claim 1  wherein at least one of the first group of planes is free of electrical and mechanical connections to the electrically conductive lining of the first plated through-hole. 
     
     
         7 . The method of  claim 1  wherein the number of the at least one of the first group of planes equals the number of the at least one of the second group of planes. 
     
     
         8 . The method of  claim 1  further comprising:
 arranging the plurality of electrically conductive layers in the multi-layer printed circuit board to minimize return current loop inductance among the electrically conductive layers included in the first and second groups of planes. 
 
     
     
         9 . The method of  claim 1 , further comprising:
 selecting the at least one of the first group of planes to be positioned within the multi-layer printed circuit board proximal to the at least one of the second group of planes with a minimum number of intervening electrically conductive layers that are free of electrical connections to the electrically conductive lining of the first or second plated through-holes.   
     
     
         10 . A method of attaching an electronic component to a multi-layer printed circuit board (PCB), the method comprising:
 positioning a first lead of an electronic component into a first plated through-hole of a PCB;   positioning a second lead of the electronic component into a second plated through-hole of the PCB;   soldering the first lead to an electrically conductive barrel of the first plated through-hole so that the first lead is electrically coupled to a first subset of a group of electrically conductive ground planes of the PCB and is free of electrical connections to a second subset of the group of electrically conductive ground planes of the PCB; and   soldering the second lead to an electrically conductive barrel of the second plated through-hole.   
     
     
         11 . The method of  claim 10 , wherein the soldering the second lead step comprises:
 electrically coupling the second lead to at least one of a group of electrically conductive power planes of the PCB.   
     
     
         12 . The method of  claim 11 , wherein the first subset of the group of electrically conductive ground panels and the at least one of the group of electrically conductive power planes are free from the second subset of the group of electrically conductive ground panels being positioned therebetween. 
     
     
         13 . The method of  claim 10 , wherein the positioning a first lead step comprises:
 inserting the first lead from a first to a second side of the PCB, wherein first subset is positioned proximate the first side of the PCB.   
     
     
         14 . The method of  claim 13 , wherein the second subset of the group of electrically conductive ground panels is positioned proximate the second side of the PCB. 
     
     
         15 . The method of  claim 13 , wherein the second subset of the group of electrically conductive ground panels is free from an overlapping relationship with the first subset of the group of electrically conductive ground panels. 
     
     
         16 . The method of  claim 13 , wherein the soldering steps utilize lead-free solder. 
     
     
         17 . A method of constructing a multi-layer printed circuit board (PCB), comprising:
 bonding together a plurality of electrically conductive layers with dielectric material disposed between the electrically conductive layers, the plurality of electrically conductive layers including a group of ground planes and a group of power planes;   forming a plurality of vias through at least some of the plurality of electrically conductive layers; and   plating each of the vias with electrically conductive material to form a plurality of electrically conductive barrels; wherein after the plating step, a first subset of one of the group of ground planes or group of power planes is electrically connected to the electrically conductive barrel of a first of the vias and a second subset of the one of the group of ground planes or group of power planes is free of electrical connections to the electrically conductive barrel of the first via.   
     
     
         18 . The method of  claim 17 , further comprising:
 inserting a lead of an electrical component into the first via; and   soldering the lead to the electrically conductive barrel of the first via.   
     
     
         19 . The method of  claim 18 , wherein the soldering step comprises:
 performing a wave soldering process.   
     
     
         20 . The method of  claim 19 , wherein the performing step comprises:
 filling a substantial entirety of the first via with a lead-free solder.