High linearity mixer and direct conversion receiver using the same

Abstract

A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.

1 . A high linearity mixer device comprising:
 a sampler unit charge-sampling an input current according to a sampling frequency; and   a buffer unit amplifying an output signal from the sampler unit while having a low input impedance, and outputting a current signal.   
     
     
         2 . The device of  claim 1 , wherein the sampler unit and the buffer unit are implemented in the form of differential circuits. 
     
     
         3 . The device of  claim 1 , wherein the sampler unit is implemented by using a switching element, and a sampling signal having the sampling frequency controls a switching operation. 
     
     
         4 . The device of  claim 3 , wherein the sampler unit is implemented in the form of a double balanced mixer. 
     
     
         5 . The device of  claim 3 , wherein the switching element is implemented by using a MOSFET, and the sampling signal is input to a control node of an amplification element. 
     
     
         6 . The device of  claim 1 , wherein the buffer unit is implemented by including a common gate amplifier for terminating the output signal from the sampler unit. 
     
     
         7 . The device of  claim 6 , wherein a current source of the common gate amplifier is implemented as an active current source or a lossy load. 
     
     
         8 . The device of  claim 6 , wherein the current source of the output stage of the common gate amplifier is implemented as a lossy load, an active current source, or a cascade current source. 
     
     
         9 . A direct conversion receiver comprising:
 a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit amplifying an output signal from the sampler unit while having a low input impedance, and outputting a current signal; and   a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.   
     
     
         10 . The receiver of  claim 9 , wherein the sampler unit and the buffer unit are implemented in the form of differential circuits. 
     
     
         11 . The receiver of  claim 9 , wherein the sampler unit is implemented by using a switching element, and a sampling signal having the sampling frequency controls a switching operation. 
     
     
         12 . The receiver of  claim 11 , wherein the sampler unit is implemented in the form of a double balanced mixer. 
     
     
         13 . The receiver of  claim 11 , wherein the switching element is implemented by using a MOSFET, and the sampling signal is input to a control node of a MOSFET. 
     
     
         14 . The receiver of  claim 9 , wherein the buffer unit is implemented by including a common gate amplifier for terminating the output signal from the sampler unit. 
     
     
         15 . The receiver of  claim 14 , wherein a current source of the common gate amplifier is implemented as an active current source or a lossy load. 
     
     
         16 . The receiver of  claim 14 , wherein the current source of the output stage of the common gate amplifier is implemented as a lossy load, an active current source, or a cascade current source. 
     
     
         17 . The receiver of  claim 9 , further comprising:
 a local oscillation device generating a signal having the sampling frequency and transmitting the generated signal to the high linearity mixer device and the filter device.   
     
     
         18 . The receiver of  claim 9 , wherein the filter device comprises:
 a signal transmission unit generating a plurality of delay signals by delaying input signals by different sampling periods and giving the same or different weighting to the signals, and outputting the generated delay signals; and   an adding unit adding the plurality of delay signals output from the signal transmission unit and outputting the results.   
     
     
         19 . The receiver of  claim 18 , wherein the signal transmission unit generates an odd number (2k−1, where k is a natural number) of delay signals and
 an m-th delay signal has the same weighting as that of a (2k−m)-th delay signal (where m is a natural number equal to or lower than k−1). 
 
     
     
         20 . The receiver of  claim 9 , wherein the filter device is implemented in the form of a differential circuit.