Digital phase locked loop with dithering

Abstract

An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

1 . An analog to digital conversion system comprising:
 an input circuit for receiving an analog signal;   a quantizer coupled to said input and operational to provide quantized digital samples of the analog signal;   a processor coupled to the quantizer being operational to receive and process said quantized digital samples; and   a dither circuit coupled to said input circuit, said dither circuit operable to generate a short sequence dither signal to perturb quantization of said analog signal.   
     
     
         2 . The system of  claim 1 , wherein the processor is operable to filter the quantized digital samples to filter out the short sequence dither signal. 
     
     
         3 . The system of  claim 2 , wherein the input circuit is a variable delay circuit, operable to produce a variable delay in the input signal by controlling a switching threshold in response to the short sequence dither signal.