Semiconductor device and manufacturing method of the same

Abstract

A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of the channel region, wherein the transistor is a memory element constituting the channel region as a floating body cell.

1 . A semiconductor device comprising:
 a semiconductor substrate;   an insulating film formed on the semiconductor substrate, the insulating film including a flat upper surface;   a silicon layer formed on the flat upper surface of the insulating film, the silicon layer including a first portion having a first upper surface, a second portion having a second upper surface and a third portion having a third upper surface and located between the first and second portions, wherein a first thickness of the silicon layer between the first upper surface in the first portion of the silicon layer and the flat upper surface of the insulating film is same as a second thickness of the silicon layer between the second upper surface in the second portion of the silicon layer and the flat upper surface of the insulating film, and a third thickness of the silicon layer between the third upper surface in the third portion of the silicon layer and the flat upper surface of the insulating film is smaller than the first thickness of the silicon layer;   a gate electrode of a floating gate body cell, formed above the third upper surface in the third portion of the silicon layer, wherein the gate electrode includes a fourth upper surface and a first and a second side walls, the first side wall has a first facing portion facing to the first portion of the silicon layer, the second side wall has a second facing portion facing to the second portion of the silicon layer, and a height of the fourth upper surface of the gate electrode is higher than a height of the first upper surface in the first portion of the silicon layer relative to the flat upper surface of the insulating film;   a drain region formed in the first portion in the first side wall of the silicon layer, the drain region facing to whole of the first facing portion in the first side wall of the gate electrode; and   a source region formed in the second portion in the second side wall of the silicon layer, the source region facing to a part of the second facing portion in the second side wall of the gate electrode,   wherein the second facing portion of the gate electrode includes a lower portion which does not face to the source region.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the drain is formed from the first upper surface in the first portion of the silicon layer to a bottom portion in the first portion of the silicon layer. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the source region is formed at the second upper surface in the second portion of the silicon layer. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the third thickness in the third portion of the silicon layer is less than 400 Angstrom. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the first side wall between the fourth upper surface and the first upper surface is covered with a first spacer film, and the second side wall between the fourth upper surface and the second upper surface is covered with a second spacer film. 
     
     
         6 . A semiconductor device comprising:
 a semiconductor substrate;   an insulating film formed on the semiconductor substrate, the insulating film including a flat upper surface;   a silicon layer formed on the flat upper surface of the insulating film, the silicon layer including a first portion having a first upper surface, a second portion having a second upper surface and a third portion having a third upper surface and located between the first and second portions, wherein a first thickness of the silicon layer between the first upper surface in the first portion of the silicon layer and the flat upper surface of the insulating film is same as a second thickness of the silicon layer between the second upper surface in the second portion of the silicon layer and the flat upper surface of the insulating film, and a third thickness of the silicon layer between the third upper surface in the third portion of the silicon layer and the flat upper surface of the insulating film is smaller than the first thickness of the silicon layer;   a gate electrode of a floating gate body cell, formed above the third upper surface in the third portion of the silicon layer, wherein the gate electrode includes a fourth upper surface and a first and a second side walls, the first side wall has a first facing portion facing to the first portion of the silicon layer, the second side wall has a second facing portion facing to the second portion of the silicon layer, and a height of the fourth upper surface of the gate electrode is higher than a height of the first upper surface in the first portion of the silicon layer relative to the flat upper surface of the insulating film;   a drain region formed in the first portion of the silicon layer, wherein a fourth thickness of the drain region relative to the first upper surface is larger than a thickness of the first facing portion in the first side wall of the gate electrode; and   a source region formed in the second portion of the silicon layer, wherein a fifth thickness of the source region relative to the second upper surface is smaller than a thickness of the second facing portion in the second side wall of the gate electrode.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the drain region is formed from the first upper surface in the first portion of the silicon layer to a bottom portion in the first portion of the silicon layer. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein the source region is formed at the second upper surface in the second portion of the silicon layer. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein the third thickness in the third portion of the silicon layer is less than 400 Angstrom. 
     
     
         10 . The semiconductor device according to  claim 6 , wherein the first side wall between the fourth upper surface and the first upper surface is covered with a first spacer film, and the second side wall between the fourth upper surface and the second upper surface is covered with a second spacer film.