Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

1 . A semiconductor memory device, comprising:
 a semiconductor substrate;   a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film;   a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less; and   a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein the metal oxide layer is included in the first insulating film. 
     
     
         3 . The semiconductor memory device according to  claim 2 , wherein the first insulating film includes a first nitride film, a first oxide film, the metal oxide layer, a second oxide film, and a second nitride film which are stacked in order. 
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein the metal oxide layer is formed on the controlling gate electrode. 
     
     
         5 . The semiconductor memory device according to  claim 1 , wherein the controlling gate electrode includes a first controlling gate electrode film, the metal oxide layer, and a second controlling gate electrode film which are stacked in order. 
     
     
         6 . The semiconductor memory device according to  claim 1 , wherein the charge storage layer includes a first charge storage film, the metal oxide layer, and a second charge storage film which are stacked in order. 
     
     
         7 . The semiconductor memory device according to  claim 6 , wherein in the word line, the gate insulating film and the charge storage layer, and a second cavity are alternately formed below the first insulating film. 
     
     
         8 . The semiconductor memory device according to  claim 7 , wherein a lower surface of the first insulating film covering the second cavity is located lower than an upper surface of the second charge storage film and higher than the metal oxide layer. 
     
     
         9 . The semiconductor memory device according to  claim 1 , wherein the second insulating film is a silicon oxynitride film. 
     
     
         10 . The semiconductor memory device according to  claim 1 , wherein the metal oxide layer includes at least any one of ZrO 2 , PbZrO 2 , BaZrO 3 , HfO 2 , HfON, HfAlO, LaO 3 , Al 2 O 3 , AIZrO 5 , Ta 2 O 5 , TiO 2 , and Y 2 O 3 . 
     
     
         11 - 20 . (canceled)