Novel method of frequency synthesis for fast switching

Abstract

A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

1 . A digital frequency synthesizer, comprising:
 a frequency multiplier coupled to at least one source for providing a digital frequency signal, wherein the frequency multiplier is configured to receive the digital frequency signal and a second multiplier input and to provide a multiplier output;   a delta sigma modulator configured to receive a fractional input and to provide a modulator output, wherein the modulator output is a sequence of integers whose average represents the fractional input, wherein the delta sigma modulator includes a clock input for receiving a clock signal, wherein the clock signal is the multiplier output signal or is derived from the multiplier output signal; and   a summer circuit configured to receive the modulator output from the delta sigma modulator and an integer input and to provide a summer output, wherein the summer output is provided as the second multiplier input to the frequency multiplier.   
     
     
         2 . The digital frequency synthesizer of  claim 1 , wherein the sequence of integers whose average represents the fractional input are all added to the integer input to generate the summer output. 
     
     
         3 . The digital frequency synthesizer of  claim 1 , wherein the digital synthesizer is utilized in a wireless communication device. 
     
     
         4 . The digital frequency synthesizer of  claim 1 , wherein wideband modulation is obtained. 
     
     
         5 . The digital frequency synthesizer of  claim 1 , wherein the multiplier output signal is provided to a clean-up phase locked loop. 
     
     
         6 . The digital frequency synthesizer of  claim 1 , wherein the digital frequency synthesizer is entirely integrated on at least one of a CMOS, bi-CMOS, silicon germanium, gallium arsenide device. 
     
     
         7 . A frequency synthesizer, comprising:
 an operator receiving a first signal at a first operator input and a sum signal at a second operator input and providing an output signal at a first output, wherein the operator is a divider or multiplier;   a summer receiving a modulator signal at a first input and an integer signal at a second summer input and providing the sum signal at a summer output; and   a modulator providing the modulator signal and receiving a fraction signal at a fraction input.   
     
     
         8 . The frequency synthesizer of  claim 7 , wherein the modulator is a delta- sigma modulator. 
     
     
         9 . The frequency synthesizer of  claim 7 , wherein wideband modulation is obtained. 
     
     
         10 . The frequency synthesizer of  claim 7 , further comprising:
 providing the output signal to a clean-up phase locked loop.   
     
     
         11 . The frequency synthesizer of  claim 7 , wherein the operator is a multiplier and the output signal is coupled to a clock input of the modulator. 
     
     
         12 . The frequency synthesizer of  claim 11 , wherein the modulator is a delta-sigma modulator. 
     
     
         13 . The frequency synthesizer of  claim 7 , wherein the operator is a divider. 
     
     
         14 . The digital frequency synthesizer of  claim 13 , wherein a multiplier is coupled to the first input. 
     
     
         15 . A digital frequency synthesizer, comprising:
 an operator receiving a sum signal and a clock signal and providing an output signal;   a control circuit providing a first signal in response to a fraction signal; and   a summer providing the sum signal in response to the first signal and frequency input.   
     
     
         16 . The digital frequency synthesizer of  claim 15 , wherein the control circuit includes a dithering circuit. 
     
     
         17 . The digital frequency synthesizer of  claim 16 , wherein the control comprises a delta-sigma modulator. 
     
     
         18 . The digital frequency synthesizer of  claim 17 , wherein wideband modulation is achieved. 
     
     
         19 . The digital frequency synthesizer of  claim 15 , wherein the operator is a multiplier. 
     
     
         20 . The digital frequency synthesizer of  claim 15 , wherein output signal is provided as a clock input to the control circuit.