Structure and Method for Placement, Sizing and Shaping of Dummy Structures

Abstract

A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

1 . A method for use in fabricating a chip comprising:
 providing at least two functional areas of a layer; and   adding at least one dummy structure to the layer within a predetermined distance to at least one of the functional areas,   wherein the adding comprises:
 determining a size for each dummy structure of the at least one dummy structure as a function of size and density of the at least two functional areas. 
   
     
     
         2 . The method according to  claim 1 , further comprising determining a shape of each dummy structure as a function of the determined size. 
     
     
         3 . The method according to  claim 1 , wherein determining the size of each dummy structure further comprises determining the size as a function of a functionality of the at least two functional areas. 
     
     
         4 . The method according to  claim 3 , further comprising determining a placement of each dummy structure as a function of a functionality of the at least two functional areas. 
     
     
         5 . The method according to  claim 1 , wherein determining the size of each dummy structure further comprises determining the size as a function of a local property of the at least two functional areas. 
     
     
         6 . The method according to  claim 1 , further comprising determining placement of each dummy structure as a function of a width of a closer one of the at least two functional areas. 
     
     
         7 . The method according to  claim 1 , further comprising determining placement of each dummy structure as a function of a width of a smaller one of the at least two functional areas. 
     
     
         8 . The method according to  claim 1 , wherein determining the size of each dummy structure further comprises determining the size as a function of a shape of one of the at least two functional areas. 
     
     
         9 . The method according to  claim 1 , wherein determining the size of each dummy structure further comprises determining the size as a function of functionality of the at least two functional areas and size of the at least two functional areas. 
     
     
         10 . The method according to  claim 1 , further comprising determining placement of each dummy structure as a function of a width of at least one of said at least two functional areas and a distance between the at least two functional areas. 
     
     
         11 . The method according to  claim 10 , wherein determining the size of each dummy structure comprises determining the size as a function of the determined placement. 
     
     
         12 . The method according to  claim 1 , wherein providing the at least two functional areas of the layer and adding the at least one dummy structure comprises fabricating a chip that includes the at least two functional areas and the at least one dummy structure. 
     
     
         13 . A chip comprising:
 a plurality of functional areas of a layer; and   a plurality of dummy structures within the layer spaced from the functional areas, wherein each dummy structure has a size that is a function of the size and density of the functional areas.   
     
     
         14 . The chip according to  claim 13 , wherein the functional areas comprise active elements. 
     
     
         15 . The chip according to  claim 13 , wherein the functional areas comprise passive elements. 
     
     
         16 . The chip according to  claim 13 , wherein the functional areas comprise conductive traces. 
     
     
         17 . The chip according to  claim 13 , wherein each dummy structure has a shape that is a function of the size. 
     
     
         18 . The chip according to  claim 13 , wherein the size of the dummy structures is also a function of a functionality of at least one of the functional areas. 
     
     
         19 . The chip according to  claim 18 , wherein each dummy structure is located at a location that is a function of the functionality of at least one of the functional areas. 
     
     
         20 . The chip according to  claim 13 , wherein the size of each dummy structure is a function of local properties of the functional areas. 
     
     
         21 . The chip according to  claim 13 , wherein each dummy structure is located at a location that is a function of a width of a closer one of the functional areas. 
     
     
         22 . The chip according to  claim 13 , wherein each dummy structure is located at a location that is a function of a width of a smaller one of the functional areas. 
     
     
         23 . The chip according to  claim 13 , wherein the size of each dummy structure is also a function of a shape of one the functional areas. 
     
     
         24 . The chip according to  claim 13 , wherein the size of each dummy structure is a function of functionality of the functional areas and size of the functional areas. 
     
     
         25 . The chip according to  claim 13 , wherein the chip comprises a microelectronic device. 
     
     
         26 . The chip according to  claim 13 , wherein the chip comprises a MEMS device.