Method and apparatus for scalable and super-scalable information processing using binary gate circuits structured by code-selected pass transistors

Abstract

A processing space comprises an array of transistors empowered by forming connections through circuit pass transistors to power and data input/output means and connections therebetween through signal pass transistors. By structuring the needed circuits at the site(s) of the data the von Neumann bottleneck is eliminated, which increases the computing power of the apparatus substantially, thus to enable non-stop Information Processing on steady streams of data and code, with no repetitive instruction and data transfers required. That code will identify the physical locations of every transistor in the processing space, and will enable only the pass transistors therein needed to structure the circuits of any arithmetical/logical algorithm in a processing space of any size, speed, and level of computer power. By joining one processing space to another the apparatus also exhibits super-scalability.

1 . A scalable and super-scalable information processing apparatus, comprising:
 At least a first processing space comprising an array of independently controllable energy transmitting information processing elements that encompass a first area having a first periphery, said information processing elements having access to power means and data input means, with said first area encompassing a planar surface of said at least a first processing space, said at least a first processing space having a pre-determined dimensionality and pressure contact means on each of a number of sides thereof that comport with said dimensionality and are disposed normally to said planar surface, with said information processing elements being disposed in rows and columns within said first area, said disposition of said information processing elements placing said information processing elements in repetitive side-by-side relationships in each said dimension;   Control means by which code may be entered into said processing spaces to bring about connections between said energy transmitting information processing elements and from said energy transmitting information processing elements to said power means and said data input means;   Wherein, by the entry of code through said control means, information processing can be rendered possible by accessing said power means and said data input means, and selectively interconnecting said energy transmitting information processing elements in such a number of directions as is defined by said dimensionality of said at least a first processing space;   Wherein having one said energy transmitting information processing element in a side-by-side relationship with another said energy transmitting information processing element forms a connection possibility, said connection possibilities being limited in number only by the number of said energy transmitting information processing elements being present; with   The number of separate connection possibilities present within said at least a first processing space establishing the computing power of said information processing apparatus; wherein   Upon making connection from said power means to said at least a first said energy transmitting information processing element and from said at least a first said energy transmitting information processing element to another said energy transmitting information processing element constitutes an information processing possibility;   Upon creating at least one said information processing possibility and entering a signal into said information processing possibility through said data input means or from a preceding information processing element, with said signal then passing on from said information processing possibility to at least one more of said energy transmitting information processing elements and eliciting a response from said at least one more energy transmitting information processing element constitutes an information processing event;   Whereby, through addition to said at least one said information processing element of an arbitrary number of more said information processing elements, said computing power of said at least a first processing space will increase accordingly,   Thus to exhibit scalability.   
     
     
         2 . The information processing apparatus of  claim 1 ; wherein
 Said energy transmitting information processing elements that lie within a row or column bordering said periphery have at least one direction in which no energy transmitting information processing element to which connection could be made is present, and is thus not able to provide a connection opportunity;   However, adding to said first processing space at least one more said processing space of like structure as said first processing space by interconnection of at least one said energy transmitting information processing element that lies within said periphery of said first processing space to a like said energy transmitting information processing element that is disposed within a periphery of said at least one more processing space will produce a composite processing space having a new area and a new periphery; and   Upon connecting said at least one more said processing space to said at least a first processing space through said energy transmitting information processing elements that lie within a row or column bordering said periphery and said pressure contact means to form said composite processing space, the number of connection opportunities present in said composite processing space will be greater than the sum of the connection opportunities in said at least a first processing space and said at least one more processing space, and consequently,   The computing power of said composite processing space will be greater than the sum of the computing powers of said at least a first processing space and said at least one more processing space, thus to exhibit super-scalability.   
     
     
         3 . Apparatus for information processing, comprising:
 An array of passive energy transmitting devices, each having a number of connectible terminals thereon disposed along directions as defined by the dimensionality of said array, each of said passive energy transmitting devices being capable of being transformed into a corresponding active energy transmitting device capable of receiving energy packets having information contained therein and performing information processing on said energy packets;   An array of active energy transmitting devices having proximal and distal ends, said active energy transmitting devices being capable of passing through energy packets upon the imposition thereto of an enabling signal, with said proximal ends of said active energy transmitting devices being connected respectively to different ones of said connectible terminals on said passive energy transmitting devices, and said distal ends of said active energy transmitting devices being connected respectively to:   An energy source, an entry location for energy packets, an energy sink, and said number of connectible terminals are disposed on at least one other of said passive energy transmitting devices; and   Addressing means by which enabling signals can be directed to selected ones of said active energy transmitting devices; whereupon   The imposition of an enabling signal onto one or more of said active energy transmitting devices connected to one or more of said passive energy transmitting devices that await the entry therein of said energy packets will transform said one or more passive energy transmitting devices into corresponding active energy transmitting devices that will perform information processing upon the entry of energy packets into said entry location for energy packets.   
     
     
         4 . The information processing apparatus of  claim 2  wherein:
 Said energy comprises electronic energy; 
 Said energy transmitting information processing elements comprise operational transistors having a number of terminals connected thereto; 
 An array of pass transistors that connect respectively between said terminals of said operational transistors and said terminals of at least one other said operational transistor, said power means, and said data input means; 
 Said power means comprises connection to V dd  on one side of said operational transistor and to GND on an opposite side of said operational transistor; 
 An array of code selectors respectively connected to said pass transistors that are connected to said operational transistor; whereby 
 An enabling of selected ones of said pass transistors would cause the structuring of an operable binary logic circuit; 
 An entry of a data bit into said operational transistors would bring about an information processing event, whereby 
 The full processing of said data would bring about the execution of an algorithm that expressed a particular arithmetical/logical problem. 
 
     
     
         5 . The information processing apparatus of  claim 4  further comprising:
 An integrated circuit having terminal lines connected to said operational transistors including circuit lines that connect to said power means and to an input/output terminal and signal lines that connect through pass transistors to terminals of said another said operational transistor; 
 Said pressure contact means comprises extensions of said Vdd, GND, and signal lines beyond the periphery of the integrated circuit sufficiently to permit a firm electrical contact to be made between said extensions of a first said integrated circuit and of at least one more integrated circuit; 
 Said signal lines render possible the joinder of one said processing space to another said processing space in electrical continuity; thereby
 To permit the occurrence of information processing events through the joinder of one said at least a first processing space to said at least one more processing space; thereby: 
 To permit the structuring of binary logic circuits both within both said at least a first processing space and said at least one more processing space and within the joinder of said at least a first processing space and said at least one more processing space; thus 
 To permit the structuring of a composite processing space of unlimited size, speed, and data handling capacity, and thereby to exhibit super-scalability. 
 
 
     
     
         6 . The information processing apparatus of  claim 5  wherein
 Said information processing apparatus is fabricated on an integrated circuit chip having four edges; and
 Each said edge comprises a cut line along which are disposed a row or column of operational transistors designated as peripheral transistors, with pass transistors connected thereto and to said terminals of said at least one more processing space, wherein 
 An enabling of said pass transistors serves both to permit the joinder of one said at least a first processing space and said at least one more processing space, and the structuring of a binary logic circuit that permits the occurrence of an information processing event; thereby 
 To permit the structuring of binary logic circuits both within said processing space and through the joinder of said at least a first processing space and said at least one more processing space; thus 
 To permit the structuring of a composite processing space of unlimited size, speed, and data handling capacity. 
 
 
     
     
         7 . The super-scalable information processing apparatus of  claim 6  wherein said energy is electronic energy, said passive energy transmitting information processing elements are operational transistors, and said active energy transmitting information processing elements are pass transistors. 
     
     
         8 . The super-scalable information processing apparatus of  claim 7  wherein, by the enabling of selected ones of said connections, binary logic circuits can be structured that are capable of receiving operational data and processing said data such that an algorithm that expresses a particular arithmetic/logical problem can be executed. 
     
     
         9 . The super-scalable information processing apparatus of  claim 8  wherein processing spaces are formed on separate integrated circuits, and said integrated circuits each comprise a first array of passive transistors and a second array of active transistors connected at proximal ends thereof to respective passive transistors, wherein respective ones of said array of active transistors also connect at distal ends thereof to an energy source, a source of external data input, and an energy sink, respectively, thus to convert said passive transistors into active transistors, and respective ones of said active transistors of said second array serve to make connection between said terminals of at least one said active transistor of at least one processing space and said terminals of another active transistor of at least one more processing space. 
     
     
         10 . The super-scalable information processing apparatus of  claim 1  further comprising;
 Code controlled switching means within said connections between said one or more of said terminals of one said processing element to one or more said terminals of an adjacent said processing element, whereby;
 By opening or closing said connections so as to structure said one or more processing elements into a desired circuit or part thereof; and 
 Providing code to said switching means that will bring about such opening or closing thereof, thus to structure desired circuits that are applicable to the execution of one or more algorithms; and 
 Employing data entrance means to enter such data as may be necessary to execute said algorithms, 
 Thus to carry out information processing.