Floating point divider and information processing apparatus using the same

Abstract

A floating point divider includes a mantissa repetitive processing unit and an operation execution control unit. The mantissa repetitive processing unit calculates a quotient and a partial remainder by a digit-recurrence process for a mantissa of a dividend of an input operand. The operation execution control unit determines a bit value at a specified position uniquely specified based on a radix of an operation execution process with respect to the partial remainder. The mantissa repetitive processing unit reduces the number of digit-recurrence processes by calculating a quotient and a remainder based on a determining result of the operation execution control unit. The number of bits of the quotient is double of that of a quotient calculated once every the digit-recurrence process. The number of left-shift processes processed on the remainder is double of that of a remainder calculated once every the digit-recurrence process.

1 . A floating point divider, which is a binary digit-recurrence floating point divider, comprising:
 a mantissa repetitive processing unit configured to calculate a quotient and a partial remainder by a digit-recurrence process for a mantissa of a dividend of an input operand; and   an operation execution control unit configured to determine a bit value at a specified position uniquely specified based on a radix of an operation execution process with respect to said partial remainder,   wherein said mantissa repetitive processing unit reduces the number of digit-recurrence processes by calculating a quotient of which the number of bits is double of that of a quotient calculated once every said digit-recurrence process and a remainder on which the number of left-shift processes is double of that of a remainder calculated once every said digit-recurrence process, based on a determining result of said operation execution control unit.   
     
     
         2 . The floating point divider according to  claim 1 , wherein said operation execution control unit outputs an advance notice signal to the outside at a timing when said digit-recurrence process ends and a rounding process starts,
 wherein said advance notice signal indicates that an operation ends after a fixed time period passes.   
     
     
         3 . The floating point divider according to  claim 2 , further comprising:
 a determining unit configured to determine whether or not all bits of said partial remainder are bit values of 0,   wherein said operation execution control unit stops said digit-recurrence process and starts said rounding process when said all bits of said partial remainder are bit values of 0, based on a determining result of said determining unit.   
     
     
         4 . The floating point divider according to  claim 2 , further comprising:
 an unordinary number detecting unit configured to detect whether or not said input operand is an unordinary number,   wherein said operation execution control unit stops said digit-recurrence process and starts said rounding process when said input operand is detected as an unordinary number, based on a detecting result of said unordinary number detecting unit.   
     
     
         5 . The floating point divider according to  claim 1 , wherein said mantissa repetitive processing unit includes:
 a 1-bit left shifter configured to shift said partial remainder to the left by 1 bit,   a 2-bit left shifter configured to shift said partial remainder to the left by 2 bits,   a first selector configured to select one of said mantissa of said dividend, said partial remainder outputted from said 1-bit left shifter and said partial remainder outputted from said 2-bit left shifter as a first partial remainder, based on a selection signal,   a subtracter configured to execute a subtraction process based on said first partial remainder and a divisor of said input operand and output a carry bit and a subtraction result, and   a second selector configured to output one of said first partial remainder and said subtraction result as said partial remainder newly based on said carry bit to said 1-bit left shifter, said 2-bit left shifter and said operation execution control unit,   wherein said mantissa repetitive processing unit outputs said bit value at said specified position to said operation execution control unit based on said partial remainder, and   wherein said operation execution control unit generates said selection signal based on said bit value of said specified position and output said selection signal to said first selector.   
     
     
         6 . The floating point divider according to  claim 1 , wherein said mantissa repetitive processing unit includes:
 a 2-bit left shifter configured to shift said partial remainder to the left by 2 bits,   a 4-bit left shifter configured to shift said partial remainder to the left by 4 bits,   a first selector configured to select one of said mantissa of said dividend, said partial remainder outputted from said 2-bit left shifter and said partial remainder outputted from said 4-bit left shifter as a first partial remainder, based on a selection signal,   a first subtracter configured to execute a subtraction process based on said first partial remainder and a divisor of said input operand and output a first carry bit and a first subtraction result,   a second subtracter configured to execute a subtraction process based on said first partial remainder and a value that said divisor of said input operand is doubled and output a second carry bit and a second subtraction result,   a third subtracter configured to execute a subtraction process based on said first partial remainder and a value that said divisor of said input operand is tripled and output a third carry bit and a third subtraction result, and   a second selector configured to output one of said first partial remainder, said first subtraction result, said second subtraction result and said third subtraction result as said partial remainder newly based on said first carry bit, said second carry bit and said third carry bit to said 2-bit left shifter, said 4-bit left shifter and said operation execution control unit,   wherein said mantissa repetitive processing unit outputs said bit value at said specified position to said operation execution control unit based on said partial remainder, and   wherein said operation execution control unit generates said selection signal based on said bit value of said specified position and output said selection signal to said first selector.   
     
     
         7 . An information processing apparatus comprising:
 a floating point divider, which is a binary digit-recurrence floating point divider,   wherein said floating point divider includes:   a mantissa repetitive processing unit configured to calculate a quotient and a partial remainder by a digit-recurrence process for a mantissa of a dividend of an input operand, and   an operation execution control unit configured to determine a bit value at a specified position uniquely specified based on a radix of an operation execution process with respect to said partial remainder,   wherein said mantissa repetitive processing unit reduces the number of digit-recurrence processes by calculating a quotient of which the number of bits is double of that of a quotient calculated once every said digit-recurrence process and a remainder on which the number of left-shift processes is double of that of a remainder calculated once every said digit-recurrence process, based on a determining result of said operation execution control unit.   
     
     
         8 . The information processing apparatus according to  claim 7 , wherein said operation execution control unit outputs an advance notice signal to the outside at a timing when said digit-recurrence process ends and a rounding process starts,
 wherein said advance notice signal indicates that an operation ends after a fixed time period passes.   
     
     
         9 . The information processing apparatus according to  claim 8 , wherein said floating point divider further includes:
 a determining unit configured to determine whether or not all bits of said partial remainder are bit values of 0,   wherein said operation execution control unit stops said digit-recurrence process and starts said rounding process when said all bits of said partial remainder are bit values of 0, based on a determining result of said determining unit.   
     
     
         10 . The information processing apparatus according to  claim 8 , wherein said floating point divider further includes:
 an unordinary number detecting unit configured to detect whether or not said input operand is an unordinary number,   wherein said operation execution control unit stops said digit-recurrence process and starts said rounding process when said input operand is detected as an unordinary number, based on a detecting result of said unordinary number detecting unit.   
     
     
         11 . The information processing apparatus according to  claim 7 , wherein said mantissa repetitive processing unit includes:
 a 1-bit left shifter configured to shift said partial remainder to the left by 1 bit,   a 2-bit left shifter configured to shift said partial remainder to the left by 2 bits,   a first selector configured to select one of said mantissa of said dividend, said partial remainder outputted from said 1-bit left shifter and said partial remainder outputted from said 2-bit left shifter as a first partial remainder, based on a selection signal,   a subtracter configured to execute a subtraction process based on said first partial remainder and a divisor of said input operand and output a carry bit and a subtraction result, and   a second selector configured to output one of said first partial remainder and said subtraction result as said partial remainder newly based on said carry bit to said 1-bit left shifter, said 2-bit left shifter and said operation execution control unit,   wherein said mantissa repetitive processing unit outputs said bit value at said specified position to said operation execution control unit based on said partial remainder, and   wherein said operation execution control unit generates said selection signal based on said bit value of said specified position and output said selection signal to said first selector.   
     
     
         12 . The information processing apparatus according to  claim 7 , wherein said mantissa repetitive processing unit includes:
 a 2-bit left shifter configured to shift said partial remainder to the left by 2 bits,   a 4-bit left shifter configured to shift said partial remainder to the left by 4 bits,   a first selector configured to select one of said mantissa of said dividend, said partial remainder outputted from said 2-bit left shifter and said partial remainder outputted from said 4-bit left shifter as a first partial remainder, based on a selection signal,   a first subtracter configured to execute a subtraction process based on said first partial remainder and a divisor of said input operand and output a first carry bit and a first subtraction result,   a second subtracter configured to execute a subtraction process based on said first partial remainder and a value that said divisor of said input operand is doubled and output a second carry bit and a second subtraction result,   a third subtracter configured to execute a subtraction process based on said first partial remainder and a value that said divisor of said input operand is tripled and output a third carry bit and a third subtraction result, and   a second selector configured to output one of said first partial remainder, said first subtraction result, said second subtraction result and said third subtraction result as said partial remainder newly based on said first carry bit, said second carry bit and said third carry bit to said 2-bit left shifter, said 4-bit left shifter and said operation execution control unit,   wherein said mantissa repetitive processing unit outputs said bit value at said specified position to said operation execution control unit based on said partial remainder, and   wherein said operation execution control unit generates said selection signal based on said bit value of said specified position and output said selection signal to said first selector.   
     
     
         13 . A floating point dividing method, which is a binary digit-recurrence floating point dividing method, comprising:
 calculating a quotient and a partial remainder by a digit-recurrence process for a mantissa of a dividend of an input operand; and   determining a bit value at a specified position uniquely specified based on a radix of an operation execution process with respect to said partial remainder,   reducing the number of digit-recurrence processes by calculating a quotient of which the number of bits is double of that of a quotient calculated once every said digit-recurrence process and a remainder on which the number of left-shift processes is double of that of a remainder calculated once every said digit-recurrence process, based on a determining result of said bit value at said specified position.   
     
     
         14 . The floating point dividing method according to  claim 13 , further comprising:
 outputting an advance notice signal to the outside at a timing when said digit-recurrence process ends and a rounding process starts,   wherein said advance notice signal indicates that an operation ends after a fixed time period passes.   
     
     
         15 . The floating point dividing method according to  claim 14 , further comprising:
 determining whether or not all bits of said partial remainder are bit values of 0, and   stopping said digit-recurrence process and starting said rounding process when said all bits of said partial remainder are bit values of 0, based on a determining result whether said all bits are bit values of 0.   
     
     
         16 . The floating point dividing method according to  claim 14 , further comprising:
 detecting whether or not said input operand is an unordinary number, and   stopping said digit-recurrence process and starting said rounding process when said input operand is detected as an unordinary number, based on a detecting result whether said input operand is an unordinary number.