Wafer and method for forming the same

Abstract

A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe line configured to be formed among the plurality of chips so as to separate each chip, and an align key line configured to be formed in one side of the wafer so as to form an align key pattern.

1 . A wafer comprising:
 a plurality of chips configured to be arranged in row and column directions on the wafer;   a scribe line configured to be formed among the plurality of chips so as to separate each chip; and   an align key line configured to be formed in one side of the wafer so as to form an align key pattern.   
     
     
         2 . The wafer according to  claim 1 , wherein each of the chips includes a radio frequency identification (RFID) chip. 
     
     
         3 . The wafer according to  claim 2 , wherein the RFID chip includes a non-volatile ferroelectric memory. 
     
     
         4 . The wafer according to  claim 1 , wherein the scribe line is isolated by a Deep Reactive Ion Etching (DRIE) process. 
     
     
         5 . The wafer according to  claim 4 , wherein the DRIE process is performed at a back side of the wafer on a basis of the align key. 
     
     
         6 . The wafer according to  claim 1 , wherein the align key line is formed in a crossing direction of two scribe lines. 
     
     
         7 . The wafer according to  claim 1 , wherein the align key line is formed in the form of a straight line at arbitrary positions of horizontal and vertical directions. 
     
     
         8 . A method for forming a wafer which includes a chip area, a scribe line for isolating the chip area, and an align key line in which an align key pattern is formed, the method comprising:
 forming the align key pattern on the align key line of a semiconductor substrate;   forming a circuit area on the chip area located at an upper part of the semiconductor substrate;   forming a passivation layer on the circuit area;   exposing the align key pattern by performing a backgrinding process at a back side of the semiconductor substrate;   forming a first trench on the semiconductor substrate formed in the scribe line, using a photoresist pattern as an etch mask; and   performing a wafer mounting process on the semiconductor substrate including the first trench.   
     
     
         9 . The method according to  claim 8 , wherein the chip area includes a plurality of radio frequency identification (RFID) chips. 
     
     
         10 . The method according to  claim 8 , wherein the forming of the align key pattern includes:
 forming a second trench on the semiconductor substrate; and   burying a filling material in the second trench.   
     
     
         11 . The method according to  claim 10 , wherein the filling material is different in color from the semiconductor substrate. 
     
     
         12 . The method according to  claim 8 , wherein the circuit area includes a metal line extended to the scribe line, and an Inter Metal Dielectric (IMD) layer. 
     
     
         13 . The method according to  claim 8 , wherein the passivation layer is formed on each of the chip area, the scribe line, and the align key line. 
     
     
         14 . The method according to  claim 8 , further comprising:
 forming a coating film over the passivation layer; and   forming a reinforcing film over the coating film.   
     
     
         15 . The method according to  claim 14 , wherein the reinforcing film includes either of a polymer layer or an aluminum foil tape. 
     
     
         16 . The method according to  claim 8 , wherein the photoresist pattern is formed on each of the chip area and the align key line of the semiconductor substrate. 
     
     
         17 . The method according to  claim 8 , wherein the first trench is formed at a back side of the semiconductor substrate by a Deep Reactive Ion Etching (DRIE) process. 
     
     
         18 . The method according to  claim 8 , wherein the first trench is etched until the passivation layer is exposed at a back side of the semiconductor substrate. 
     
     
         19 . The method according to  claim 8 , wherein the mounting process includes:
 forming a ring film to which the semiconductor substrate including the first trench is mounted; and   forming a ring mount around the ring film.   
     
     
         20 . The method according to  claim 8 , further comprising:
 after performing the mounting process, removing a coating film formed on the passivation layer, and removing a reinforcing film.   
     
     
         21 . A method for forming a wafer which includes a chip area, a scribe line for isolating the chip area, and an align key line in which an align key pattern is formed, the method comprising:
 forming a circuit area on the chip area located at an upper part of a semiconductor substrate;   forming the align key pattern on the align key line of a semiconductor substrate;   forming a passivation layer on the circuit area;   exposing the align key pattern by performing a backgrinding process at a back side of the semiconductor substrate;   forming a first trench on the semiconductor substrate formed in the scribe line, using a photoresist pattern as an etch mask; and   performing a wafer mounting process on the semiconductor substrate including the first trench.   
     
     
         22 . The method according to  claim 21 , wherein the forming of the align key pattern includes:
 forming a second trench at an upper part of the semiconductor substrate by etching an Inter Metal Dielectric (IMD) layer formed on the align key line;   forming a third trench coupled to the second trench by etching the semiconductor substrate at the align key line; and   burying a filling material in each of the second trench and the third trench.   
     
     
         23 . The method according to  claim 22 , wherein the filling material is different in color from the semiconductor substrate. 
     
     
         24 . The method according to  claim 21 , wherein the chip area includes a plurality of radio frequency identification (RFID) chips. 
     
     
         25 . The method according to  claim 21 , wherein the passivation layer is formed on each of the chip area, the scribe line, and the align key line. 
     
     
         26 . The method according to  claim 21 , further comprising:
 forming a coating film on the passivation layer; and   forming a reinforcing film on the coating film.   
     
     
         27 . The method according to  claim 21 , wherein the photoresist pattern is formed on each of the chip area and the align key line of the semiconductor substrate. 
     
     
         28 . The method according to  claim 21 , wherein the first trench is formed at a back side of the semiconductor substrate by a Deep Reactive Ion Etching (DRIE) process. 
     
     
         29 . The method according to  claim 21 , wherein the mounting process includes:
 forming a ring film to which the semiconductor substrate including the first trench is mounted; and   forming a ring mount along an outline of the ring film.   
     
     
         30 . The method according to  claim 21 , further comprising:
 after performing the mounting process, removing a coating film formed on the passivation layer, and removing a reinforcing film.