Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus

Abstract

A mapping apparatus maps, on a semiconductor integrated circuit, a circuit function described in a circuit description, the semiconductor integrated circuit having a plurality of reconfigurable cores arranged separately from one another and having a logic reconfiguration function. A first group of register circuits are formed between at least two reconfigurable cores included in the plurality of reconfigurable cores and temporarily hold an output from one of the reconfigurable cores and transferring the output to another one of the reconfigurable cores. The mapping apparatus includes a divider that divides the circuit function into a plurality of circuit function blocks, an eliminator that eliminates a register from between the plurality of circuit function blocks and a synthesis executer that executes logic synthesis on each of the plurality of circuit function blocks from between which the register has been eliminated. A placing and routing unit places and routes, on each of the reconfigurable cores, each of the plurality of circuit function blocks on which the logic synthesis has been executed.

1 . A mapping apparatus that maps, on a semiconductor integrated circuit, a circuit function described in a circuit description, the semiconductor integrated circuit including a plurality of reconfigurable cores arranged separately from one another and having a logic reconfiguration function and a first group of register circuits formed between at least two reconfigurable cores of the plurality of reconfigurable cores, the first group of register circuits temporarily holding an output from one of the reconfigurable cores and transferring the output to another one of the reconfigurable cores, said mapping apparatus comprising:
 a divider configured to divide the circuit function into a plurality of circuit function blocks;   an eliminator configured to eliminate a register from between the plurality of circuit function blocks;   a synthesis executer configured to execute logic synthesis on each of the plurality of circuit function blocks from between which the register has been eliminated; and   a placing and routing unit configured to place and route, on each of said reconfigurable cores, each of the plurality of circuit function blocks on which the logic synthesis has been executed.   
     
     
         2 . A program transformation apparatus that transforms a circuit description in which a circuit function of a circuit including a plurality of modules is described, said program transformation apparatus comprising:
 a calculator configured to calculate, according to the circuit description, a constraint of an input signal and an output signal of the circuit;   a generator configured to generate a plurality of patterns in which a register is or is not inserted between the plurality of modules;   an extractor configured to extract, of the generated plurality of patterns, at least one pattern that fulfills the constraint; and   a selector configured to select one of the at least one extracted patterns and to output the selected pattern as a transformed circuit description.   
     
     
         3 . The program transformation apparatus according to  claim 2 , further comprising:
 a feedback extractor configured to extract, of said plurality of modules, a plurality of modules that form a feedback system,   wherein said generator, handling the plurality of modules extracted by said feedback extractor unit as a single module, is configured to generate a plurality of patterns in which a register is or is not inserted between the modules.   
     
     
         4 . A mapping method executed in a mapping apparatus for mapping, on a semiconductor integrated circuit, a circuit function described in a circuit description, the semiconductor integrated circuit including a plurality of reconfigurable cores arranged separately from one another and having a logic reconfiguration function and a first group of register circuits formed between at least two reconfigurable cores of the plurality of reconfigurable cores, the first group of register circuits temporarily holding an output from one of the reconfigurable cores and transferring the output to another one of the reconfigurable cores, the mapping method comprising:
 dividing the circuit function into a plurality of circuit function blocks;   eliminating a register from between the circuit function blocks;   executing logic synthesis on each of the plurality of circuit function blocks from between which the register has been eliminated; and   placing and routing, on each of the reconfigurable cores, each of the plurality of circuit function blocks on which the logic synthesis has been executed.   
     
     
         5 . A program transformation method to be executed in a program transformation apparatus that transforms a circuit description in which a circuit function of a circuit including a plurality of modules is described, the program transformation method comprising:
 calculating, according to the circuit description, a constraint of an input signal and an output signal of the circuit;   generating a plurality of patterns in which a register is or is not inserted between the plurality of modules;   extracting, of the generated plurality of patterns, at least one pattern that fulfills the constraint; and   selecting one of the at least one extracted patterns and outputting the selected pattern as a transformed circuit description.