FPGA Co-Processor For Accelerated Computation

Abstract

A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA. A mechanical and electrical interface is for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard. After completion of a start-up cycle, the FPGA is configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.

1 . An accelerator module, comprising:
 a Field Programmable Gate Array (“FPGA”)   a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA;   a non-volatile memory coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA; and   a mechanical and electrical interface for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard;   the FPGA after completion of a start-up cycle being configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.   
     
     
         2 . The accelerator module according to  claim 1 , wherein the microprocessor bus is a point-to-point bus. 
     
     
         3 . The accelerator module according to  claim 2 , wherein the FPGA after completion of the start-up cycle is configured for direct communication with resources associated with the motherboard in addition to the at least one microprocessor, wherein the resources are directly accessible by the FPGA via the point-to-point bus, the point-to-point bus being a Hypertransport bus. 
     
     
         4 . The accelerator module according to  claim 3 , wherein the FPGA after completion of the start-up cycle is further configured for direct communication via a dedicated bus with dynamic random access memory forming a portion of the resources associated with the motherboard. 
     
     
         5 . The accelerator module according to  claim 2 , wherein the FPGA after completion of the start-up cycle is further configured for direct communication with resources associated with the motherboard in addition to the at least one microprocessor, wherein the resources include random access memory which is directly accessible by the FPGA via a dedicated memory bus. 
     
     
         6 . The accelerator module according to  claim 5 , wherein the random access memory is Dynamic Random Access Memory (“DRAM”). 
     
     
         7 . The accelerator module according to  claim 1 , wherein the FPGA after completion of the start-up cycle is configured for direct communication with system memory coupled to the motherboard which is associated with the microprocessor point-to-point bus to which the microprocessor socket is coupled. 
     
     
         8 . The accelerator module according to  claim 1 , further comprising Static Random Access Memory (“SRAM”) coupled to the FPGA and configured for storing configuration information for configuring at least a user programmable logic portion of the FPGA. 
     
     
         9 - 32 . (canceled) 
     
     
         33 . An accelerator system, comprising:
 a first motherboard having accelerator modules;   a second motherboard having at least one microprocessor;   each of the accelerator modules including:
 a Field Programmable Gate Array (“FPGA”) 
 a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA; 
 a non-volatile memory coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA; and 
 a mechanical and electrical interface configured for being plugged into a microprocessor socket of the first motherboard for direct communication as between the accelerator modules; 
 the microprocessor socket being coupled to a microprocessor bus for the direct communication between the accelerator modules. 
   
     
     
         34 . The accelerator system according to  claim 33 , wherein the microprocessor bus is a point-to-point bus. 
     
     
         35 . The accelerator system according to  claim 34 , wherein the microprocessor bus is a Hypertransport bus.