Semiconductor device and shift register circuit

Abstract

A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

1 . A semiconductor device comprising:
 a plurality of first transistors connected in series between predetermined first and second nodes, said plurality of first transistors each having a control electrode connected to each other, wherein each of connection nodes between said plurality of first transistors is a third node, and when said control electrode changes from an H (High) level higher than a threshold voltage of said plurality of first transistors where each of said first to third nodes and said control electrode is the H level to an L (low) level lower than said threshold voltage while said first and second nodes are kept at the H level, said third node is pulled down to the L level accordingly; and   a diode connected between said control electrode and said third node such that said control electrode serves as a cathode and said third node serves as an anode, as means for pulling down said third node in level.   
     
     
         2 . A shift register comprising:
 an input terminal, an output terminal, a first clock terminal and a reset terminal;   a first transistor configured to supply a first clock signal received at said first clock terminal to said output terminal;   a second transistor configured to discharge said output terminal;   a charging circuit configured to charge a first node to which a control electrode of said first transistor is connected, in accordance with an input signal received at said input terminal;   a discharging circuit configured to discharge said first node in accordance with a reset signal received at said reset terminal, wherein said charging circuit includes a plurality of third transistors connected in series between said first node and a power terminal and having control electrodes connected in common to said input terminal; and   a diode connected between each connection node of said plurality of third transistors and said input terminal such that said input terminal serves as a cathode and said connection node serves as an anode.   
     
     
         3 . A shift register comprising:
 first and second input terminals, an output terminal, a first clock terminal and a reset terminal;   a first transistor configured to supply a first clock signal received at said first clock terminal to said output terminal;   a second transistor configured to discharge said output terminal;   a first charging circuit configured to charge a first node to which a control electrode of said first transistor is connected;   a first discharging circuit configured to discharge said first node in accordance with a reset signal received at said reset terminal, wherein said first charging circuit includes:
 a plurality of third transistors connected in series between said first node and a power terminal and having control electrodes connected in common to a predetermined second node, 
 a second charging circuit configured to charge said second node in accordance with a first input signal received at said first input terminal, 
 a step-up circuit configured to step-up said second node in accordance with a second input signal received at said second input terminal, and 
 a second discharging circuit configured to discharge said second node in accordance with said reset signal; and 
   a diode connected between each connection node of said plurality of third transistors and said second node such that said second node serves as a cathode and said connection node serves as an anode.   
     
     
         4 . A shift register comprising:
 first and second input terminals, an output terminal, a first clock terminal and a reset terminal;   a first transistor configured to supply a first clock signal received at said first clock terminal to said output terminal;   a second transistor configured to discharge said output terminal;   a first charging circuit configured to charge a first node to which a control electrode of said first transistor is connected;   a first discharging circuit configured to discharge said first node in accordance with a reset signal received at said reset terminal, wherein said first charging circuit includes:
 a plurality of third transistors connected in series between said first node and a power terminal and having control electrodes connected in common to a predetermined second node, 
 a second charging circuit configured to charge said second node in accordance with a first input signal received at said first input terminal, 
 a step-up circuit configured to step-up said second node in accordance with a second input signal received at said second input terminal, and 
 a second discharging circuit configured to discharge said second node in accordance with said reset signal, wherein 
   said second charging circuit includes a plurality of seventh transistors connected in series between said second node and a power terminal and having control electrodes connected in common to said first input terminal; and   a diode connected between each connection node of said plurality of seventh transistors and said first input terminal such that said first input terminal serves as a cathode and said connection node serves as an anode.   
     
     
         5 . A shift register comprising:
 first and second input terminals, an output terminal and a clock terminal;   first and second voltage signal terminals respectively receiving first and second voltage signals complementary to each other;   a first transistor configured to supply a clock signal received at said clock terminal to said output terminal;   a second transistor configured to discharge said output terminal;   a first driving circuit configured to supply said first voltage signal to a first node to which a control electrode of said first transistor is connected, on the basis of a first input signal received at said first input terminal;   a second driving circuit configured to supply said second voltage signal to said first node, on the basis of a second input signal received at said second input terminal;   an inverter with said first node serving as its input node and a second node connected to a control electrode of said second transistor serving as its output node, wherein   said first driving circuit includes a plurality of third transistors connected in series between said first node and said first voltage signal terminal and having control electrodes connected in common to said first input terminal, and   a second driving circuit includes a plurality of fourth transistors connected in series between said first node and said second voltage signal terminal and having control electrodes connected in common to said second input terminal;   a first diode connected between each connection node between said plurality of third transistors and said first input terminal such that said first input terminal serves as a cathode and each connection node between said plurality of third transistors serves as an anode; and   a second diode connected between each connection node between said plurality of fourth transistors and said second input terminal such that said second input terminal serves as a cathode and each connection node between said plurality of fourth transistors serves as an anode.