Non-volatile semiconductor memory device

Abstract

The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time.

1 - 8 . (canceled) 
     
     
         9 . A non-volatile semiconductor memory device comprising:
 a memory cell array having a plurality of non-volatile memory cells, the memory cell array being divided into a plurality of first erase units respectively including a plurality of second erase units; and   a control circuit which executes erase and write operations of each selected memory cell in the memory cell array in accordance with erase or write instructions,   wherein the control circuit includes a first erase control unit which performs an erase in the first erase unit and a second erase control unit which performs an erase in the second erase unit, and   wherein the first erase control unit changes an electrical charge accumulated in the memory cell at the erase in the first erase unit,   wherein the second erase control unit shifts the threshold voltage criterion to judge erase state at the erase in the second erase unit.   
     
     
         10 . The non-volatile semiconductor memory device according to  claim 9 ,
 wherein the memory cells of the memory cell array are arranged over a well region in matrix form,   wherein the first erase units are of well units, and wherein the second erase units are of word lines arranged corresponding to memory cell rows.   
     
     
         11 . The non-volatile semiconductor memory device according to  claim 9 ,
 wherein the memory cell array is divided into a plurality of blocks each having sectors including a plurality of memory cell rows respectively,   wherein the first erase units are of the blocks, and wherein the second erase units are of the sectors.