Reading array cell with matched reference cell

Abstract

A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

1 . A non-volatile memory (“NVM”) device comprising a multi-charge-storage-region reference cell; and wherein said device is adapted to program two storage regions of said reference cell. 
     
     
         2 . The device according to  claim 1 , wherein charge in a first charge storage region influences reading of a second charge storage region. 
     
     
         3 . The device according to  claim 1 , wherein said reference cell stores charge in a non-nitride layer. 
     
     
         4 . The device according to  claim 1 , wherein said reference cell stores charge in a charge trapping layer. 
     
     
         5 . The device according to  claim 4 , wherein said reference cell is a charge trapping type NVM device. 
     
     
         6 . The device according to  claim 5 , wherein said reference cell is a nitride read only memory (NROM) cell. 
     
     
         7 . The device according to  claim 1 , wherein the charge storage regions of said reference cell are physically separated. 
     
     
         8 . The device according to  claim 1 , wherein each of the charge storage regions is adapted to be charged to a difference threshold level. 
     
     
         9 . The device according to  claim 8 , wherein said reference cell is adapted for reading each of at least two charge storage regions individually. 
     
     
         10 . A non-volatile memory (“NVM”) device comprising a set of multi-charge-storage-region reference cells, wherein said device is adapted to program two or more storage regions of each reference cell in the set. 
     
     
         11 . The device according to  claim 10 , wherein said reference cells store charge in a non-nitride layer. 
     
     
         12 . The device according to  claim 10 , wherein said reference cells store charge in a charge trapping layer. 
     
     
         13 . The device according to  claim 10 , wherein the charge storage regions of said reference cell are physically separated. 
     
     
         14 . The device according to  claim 10 , wherein each of the charge storage regions in each cell is adapted to be charged to a difference threshold level. 
     
     
         15 . The device according to  claim 14 , wherein said reference cells are adapted for reading each of at least two charge storage regions individually. 
     
     
         16 . A method of fabricating a Non-volatile memory (“NVM”) device, said method comprising: forming on a substrate two or more multi-charge-storage-region reference cells, such that charge storage regions on each of the two or more reference cell are physically separated.