Reservoir capacitor of semiconductor device and method for fabricating the same

Abstract

A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material.

1 . A method for fabricating a semiconductor device, the method comprising:
 providing a semiconductor substrate including a first peripheral circuit region and a second peripheral circuit region;   forming a gate over a semiconductor substrate in the second peripheral circuit region;   forming an interlayer insulating film on the entire the semiconductor device including the gate;   etching the interlayer insulating film in the second peripheral circuit region to form a bit line contact hole;   forming a bit line material and a sacrificial film over the interlayer insulating film including the bit line contact hole; and   etching the sacrificial film in the first peripheral circuit region to form a trench in the first peripheral circuit region, the trench exposing the bit line material.   
     
     
         2 . The method according to  claim 1 , further comprising:
 forming a gate material in the first peripheral circuit region while the gate is being formed in the second peripheral circuit region.   
     
     
         3 . The method according to  claim 2 , wherein the gate material in the first peripheral circuit region forms of a Metal oxide Semiconductor (MOS) capacitor. 
     
     
         4 . The method according to  claim 1 , further comprising patterning the bit line material in the second peripheral circuit region to form a bit line pad. 
     
     
         5 . The method according to  claim 1 , wherein the bit line material has a stack structure including a barrier metal layer, a tungsten layer and a hard mask nitride film. 
     
     
         6 . The method according to  claim 1 , wherein the trench defines a reservoir capacitor region. 
     
     
         7 . The method according to  claim 1 , further comprising forming a conductive layer in the trench to form a reservoir capacitor. 
     
     
         8 . A method for fabricating a semiconductor device, the method comprising:
 providing a semiconductor substrate including a cell region, a first peripheral circuit region and a second peripheral circuit region;   forming a buried cell gate and landing plug contact in the semiconductor substrate in the cell region;   forming a gate material over the semiconductor substrate in the first and second peripheral circuit regions;   patterning the gate material in the second peripheral circuit region to form a peri-gate;   forming a storage node contact and a bit line in the cell region each of which is electrically coupled with the landing plug contact in the cell region;   forming an interlayer insulating film over the semiconductor substrate including the bit line and the storage node contact of the cell region, over the gate material of the first peripheral circuit region and over the semiconductor substrate including the peri-gate in the second peripheral circuit region;   etching the interlayer insulating film to form a peri-bit line contact hole exposing the peri-gate;   forming a bit line material in the peri-bit line contact hole over the semiconductor substrate in the first peripheral circuit region;   patterning the bit line material in the second peripheral circuit region to form a bit line pad;   forming a sacrificial film over the interlayer insulating film in the cell region, over the bit line material in the first peripheral circuit region and over the bit line pad in the second peripheral circuit region; and   etching the sacrificial film in the first peripheral circuit region and in the cell region to form a cell trench exposing the storage node contact in the cell region and form a peri-trench exposing the bit line material in the first peripheral circuit region.   
     
     
         9 . The method according to  claim 8 , wherein the gate material in the first peripheral circuit region defines part of a MOS capacitor. 
     
     
         10 . The method according to  claim 8 , wherein the bit line material has a stack structure including a barrier metal layer, a tungsten layer and a hard mask nitride film. 
     
     
         11 . The method according to  claim 8 , wherein the cell trench formed in the cell region defines a storage node region. 
     
     
         12 . The method according to  claim 8 , wherein the peri trench formed in the first peripheral circuit region defines a reservoir capacitor region. 
     
     
         13 . The method according to  claim 8 , further comprising forming a conductive layer in the cell trench and peri trench to form a storage node, thereby forming a reservoir capacitor. 
     
     
         14 . A reservoir capacitor of a semiconductor device, the reservoir capacitor comprising:
 a semiconductor substrate comprising a first peripheral circuit region and a second peripheral circuit region;   a gate formed over the semiconductor substrate in the second peripheral circuit region;   a bit line pad formed over the gate to be electrically coupled to the gate;   a bit line material formed in the first peripheral circuit region of the same layer as the bit line pad; and   a trench formed to exposed the bit line material in the first peripheral circuit region.   
     
     
         15 . The reservoir capacitor according to  claim 14 , wherein the trench formed in the first peripheral circuit region defines a reservoir capacitor region. 
     
     
         16 . The reservoir capacitor according to  claim 14 , further comprising a MOS capacitor formed under the trench in the first peripheral circuit region,
 wherein the MOS capacitor is formed of the same material as the gate.   
     
     
         17 . The reservoir capacitor according to  claim 16 , wherein the gate in the second peripheral circuit region and the MOS capacitor in the first peripheral circuit region has a deposition structure including a gate oxide, a gate poly silicon and a hard mask. 
     
     
         18 . The reservoir capacitor according to  claim 14 , further comprising forming a conductive layer in the trench. 
     
     
         19 . The reservoir capacitor according to  claim 14 , wherein the bit line pad has a deposition structure including a barrier metal layer, a tungsten layer and a hard mask nitride film. 
     
     
         20 . A semiconductor device comprising:
 a first peripheral circuit region and a second peripheral circuit region,   wherein the first peripheral circuit region comprises:   a metal-oxide-semiconductor (MOS) capacitor pattern formed over a substrate; and   a reservoir capacitor pattern formed over the MOS capacitor pattern, and   wherein the second peripheral circuit region comprises:   a gate formed over the substrate; and   a bit line pad formed over the gate to be electrically coupled to the gate, and   wherein the reservoir capacitor pad is formed at the substantially same level as the bit line pad formed in the second peripheral circuit region.