Semiconductor memory

Abstract

In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.

1 .- 5 . (canceled) 
     
     
         6 . A semiconductor memory mounted on a semiconductor device for correcting an error in data to be inputted thereto/outputted therefrom and storing such data, the semiconductor memory comprising:
 a plurality of memory cell arrays each for storing data;   at least one control terminal for receiving a read control signal for controlling a read operation of reading data from the memory cell array and a write control signal for controlling a write operation of writing data to the memory cell array;   a data input/output terminal; and   a computing unit for performing arithmetic processing on data of the memory cell array and data inputted from the data input/output terminal, wherein   one of operations among outputting data from the memory cell array to the data input/output terminal, writing data inputted from the data input/output terminal to the memory cell array, and writing a result of the arithmetic processing performed by the computing unit to the memory cell array is performed according to the read control signal and the write control signal.   
     
     
         7 . The semiconductor memory according to  claim 6 , wherein
 data from the memory cell array is outputted to the data input/output terminal when the read control signal is at a first potential and the write control signal is at a second potential,   data inputted from the data input/output terminal is written to the memory cell array when the read control signal is at the second potential and the write control signal is at the first potential, and   the result of the arithmetic processing performed by the computing unit is written to the memory cell array when the read control signal and the write control signal are at the second potential.   
     
     
         8 . The semiconductor memory according to  claim 7 , wherein
 the semiconductor memory is for operating in synchronization with external clocks, so that   when the read control signal and the write control signal are at the second potential, data stored in the memory cell array is read during a period of a first clock of the external clocks and the result of the arithmetic processing performed by the computing unit is written to the memory cell array during a period of a second clock subsequent to the first clock.   
     
     
         9 . The semiconductor memory according to  claim 6 , wherein the computing unit is for performing an EXOR operation. 
     
     
         10 . The semiconductor memory according to  claim 6 , wherein
 the control terminal includes a read control terminal for receiving the read control signal and a write control terminal for receiving the write control signal.   
     
     
         11 . The semiconductor memory according to  claim 6 , wherein
 an inversion write control signal can be inputted to the control terminal, and   one of the operations among outputting data from the memory cell array to the data input/output terminal, writing data inputted from the data input/output terminal to the memory cell array, and writing a result of the arithmetic processing performed by the computing unit to the memory cell array can be performed according to the read control signal, the write control signal and the inversion write control signal.   
     
     
         12 . The semiconductor memory according to  claim 11 , wherein
 data from the memory cell array can be outputted to the data input/output terminal when the read control signal is at a first potential and the write control signal and the inversion write control signal are at a second potential,   data inputted from the data input/output terminal can be written to the memory cell array when the read control signal and the inversion write control signal are at the second potential and the write control signal is at the first potential, and   the result of the arithmetic processing performed by the computing unit can be written to the memory cell array when the read control signal and the write control signal are at the second potential and the inversion write control signal is at the first potential.   
     
     
         13 . The semiconductor memory according to  claim 11 , wherein
 the control terminal includes a read control terminal for receiving the read control signal, a write control terminal for receiving the write control signal, and an inversion write control terminal for receiving the inversion write control signal.