Electrodepositing a metal in integrated circuit applications

Abstract

A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.

1 . A method for the application of metal in which the following method steps are performed without any restriction by the order specified:
 production of a contact hole to an interconnect in an insulating layer or an integrated circuit arrangement,   application of a barrier layer after the production of the contact hole,   application of a metal or a metal alloy with the aid of a galvanic method,   the barrier layer serving as a boundary electrode in the galvanic method for the application of the metal or the metal alloy,   or, in addition to the barrier layer, before the application of the radiation-sensitive layer, a boundary electrode layer being applied having a different material composition than the barrier layer, wherein a solution used for the galvanic method contains copper ions, and   wherein the solution is free of a reducing agent.   
     
     
         2 . The method as claimed in  claim 1 , characterized by the following steps:
 application of a radiation-sensitive layer after the application of the barrier layer,   irradiation of the radiation-sensitive layer in accordance with a pattern,   development of the radiation-sensitive layer after the irradiation,   removal of residues of the radiation-sensitive layer after the application of the metal.   
     
     
         3 . The method as claimed in  claim 1 , wherein the atoms of the metal have a large diffusion coefficient in silicon,
 or wherein in the metal alloy more than 50 of the atoms have a large diffusion coefficient in silicon.   
     
     
         4 . The method as claimed in one of  claim 1 , wherein the galvanic method is carried out using an external current or voltage source. 
     
     
         5 . The method as claimed in one of  claim 1 , wherein the galvanic method is carried out in a manner free of external current. 
     
     
         6 . The method as claimed in  claim 1 , wherein the solution is prepared on the basis of water, alcohol, ether or a mixture of said substances. 
     
     
         7 . The method as claimed in  claim 6 , wherein the electrolyte solution is of formaldehyde. 
     
     
         8 . The method as claimed in  claim 1 , wherein the boundary electrode layer is completely decomposed, or decomposed as far as a partial layer, during the galvanic method,
 wherein the barrier layer is decomposed in a partial layer during the galvanic method.   
     
     
         9 . The method as claimed in  claim 1 , wherein, after the removal of the radiation-sensitive layer, an etching operation is carried out in which the barrier layer is etched in accordance with the metal structures produced. 
     
     
         10 . The method as claimed in  claim 9  wherein the barrier layer is etched in accordance with the metal structures produced in a wet-chemical etching process or without carrying out a further lithographic method. 
     
     
         11 . The method as claimed in  claim 1 , wherein the interconnect comprises aluminum or an aluminum alloy. 
     
     
         12 . The method as claimed in  claim 1 , wherein the barrier layer contains a metal having a melting point of greater than 1600° C.,
 or wherein the barrier layer contains a metal whose atoms have a small diffusion coefficient in silicon, 
 or wherein the barrier layer contains a nitride, or wherein the barrier layer comprises a nitride, 
 or wherein the barrier layer contains one or more of the substances tungsten, nickel, tantalum, tantalum nitride, titanium or titanium nitride, 
 or wherein the boundary electrode layer comprises aluminum or an aluminum alloy. 
 
     
     
         13 . The method as claimed in  claim 1 , wherein the metal is copper, gold, silver or platinum,
 or wherein the metal alloy contains more than 40% by weight of at least one of said substances.   
     
     
         14 . The method as claimed in  claim 1 , wherein the contact hole has a diameter of greater than 1 μm,
 or wherein the layer thickness of the galvanic layer is greater than 100 nm. 
 
     
     
         15 . The method as claimed in  claim 1 , wherein the diffusion coefficient of the atoms of the metal or of atoms of the metal alloy in silicon at 400° C. is greater than 10 −12  cm 2 /s. 
     
     
         16 . The use of the method as claimed in  claim 1  for fabricating an integrated circuit arrangement which switches currents of greater than  1 A,
 or the use of the method for fabricating a multiplicity of carrier circuits and carried circuits, in each case at least one carried circuit being arranged on a carrier circuit, and sides with active components being assigned to one another using a chip rapid mounting technique. 
 
     
     
         17 . The use of the method as claimed in  claim 1 , wherein sides with active components are assigned to one another by soldering the carried circuit and the carrier circuit. 
     
     
         18 . An integrated circuit arrangement fabricated by the method of  claim 1 ,
 having a contact hole filled with a metal or a metal alloy,   wherein the metal or the metal alloy has, completely or within a partial layer, a crystal lattice homogeneity as is produced during a galvanic deposition method free of external current.