Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

1 . A semiconductor device comprising:
 (a) a semiconductor chip having a first main surface with a source electrode of a power MOSFET thereover and a second main surface with a drain electrode of the power MOSFET thereover;   (b) a virtually rectangular cell region provided almost in the center of the first main surface, a peripheral side region provided along each side of the cell region, and a peripheral corner region provided in each corner of the cell region;   (c) a first-conductivity type drift region provided in virtually whole surfaces of the cell region, each peripheral side region, and each peripheral corner region over the first main surface of the semiconductor chip;   (d) a first super junction structure provided in the drift region over a virtually whole surface of the cell region, having a first orientation;   (e) a second and a third super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in a direction perpendicular to the first orientation of the first super junction structure, having almost the same length and orientation as the first super junction structure; and   (f) a fourth and a fifth super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in the first orientation of the first super junction structure, having an orientation almost perpendicular to the first super junction structure.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first to fifth super junction structures are of a trench epitaxial buried type. 
     
     
         3 . The semiconductor device according to  claim 2 , further comprising:
 (g) virtually L-shaped columns each interconnecting a pair of columns configuring the second to fifth super junction structures in each peripheral corner region.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein each of the virtually L-shaped columns forms a continuous pattern with a virtually orthogonal bend at a middle point. 
     
     
         5 . The semiconductor device according to  claim 3 , wherein each of the virtually L-shaped columns forms a pattern with a pair of columns separated at a middle point and oriented perpendicularly to each other. 
     
     
         6 . The semiconductor device according to  claim 3 , wherein each of the virtually L-shaped columns comprises a pattern with a pair of columns separated at a middle point and oriented perpendicularly to each other, and an auxiliary column located near and outside a point where the paired columns meet. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein a surface resurf region is provided in at least part of each peripheral side region or each peripheral corner region in a surface region of the drift region on the first main surface side so as to surround the cell region. 
     
     
         8 . The semiconductor device according to  claim 7 , wherein a field plate extends above part of the surface resurf region. 
     
     
         9 . The semiconductor device according to  claim 7 , wherein one or a plurality of floating field rings are provided in at least part of each peripheral side region or each peripheral corner region in a surface region of the drift region on the first main surface side so as to surround the cell region. 
     
     
         10 . The semiconductor device according to  claim 7 , wherein the surface resurf region is divided into a plurality of regions. 
     
     
         11 . A semiconductor device comprising:
 (a) a semiconductor chip having a first main surface with a source electrode of a power MOSFET thereover and a second main surface with a drain electrode of the power MOSFET thereover;   (b) a virtually rectangular cell region provided almost in the center of the first main surface, a peripheral side region provided along each side of the cell region, and a peripheral corner region provided in each corner of the cell region;   (c) a first-conductivity type drift region provided in virtually whole surfaces of the cell region, each peripheral side region, and each peripheral corner region over the first main surface of the semiconductor chip;   (d) a first super junction structure provided in the drift region over a virtually whole surface of the cell region, having a first orientation;   (e) a second and a third super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in the first orientation of the first super junction structure, having almost the same orientation as the first super junction structure; and   (f) a fourth and a fifth super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in a direction perpendicular to the first orientation of the first super junction structure, having an orientation almost perpendicular to the first super junction structure.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein the second and third super junction structures are coupled to the first super junction structure. 
     
     
         13 . The semiconductor device according to  claim 12 , wherein the first to fifth super junction structures are of a trench epitaxial buried type. 
     
     
         14 . The semiconductor device according to  claim 13 , wherein the fourth and fifth super junction structures are provided across each peripheral corner region. 
     
     
         15 . The semiconductor device according to  claim 11 , wherein a surface resurf region is provided in at least part of each peripheral side region or each peripheral corner region in a surface region of the drift region on the first main surface side so as to surround the cell region. 
     
     
         16 . The semiconductor device according to  claim 15 , wherein a field plate extends above part of the surface resurf region. 
     
     
         17 . The semiconductor device according to  claim 15 , wherein one or a plurality of floating field rings are provided in at least part of each peripheral side region or each peripheral corner region in a surface region of the drift region on the first main surface side so as to surround the cell region. 
     
     
         18 . The semiconductor device according to  claim 15 , wherein the surface resurf region is divided into a plurality of regions. 
     
     
         19 . A method for manufacturing a semiconductor device, the semiconductor device comprising:
 (a) a semiconductor chip region over a wafer having a first main surface with a source electrode of a power MOSFET thereover and a second main surface with a drain electrode of the power MOSFET thereover;   (b) a virtually rectangular cell region provided almost in the center of the first main surface, a peripheral side region provided along each side of the cell region, and a peripheral corner region provided in each corner of the cell region;   (c) a first-conductivity type drift region provided in virtually whole surfaces of the cell region, each peripheral side region, and each peripheral corner region over the first main surface of the semiconductor chip;   (d) a first super junction structure provided in the drift region over a virtually whole surface of the cell region, having a first orientation;   (e) a second and a third super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in a direction perpendicular to the first orientation of the first super junction structure, having almost the same length and orientation as the first super junction structure; and   (f) a fourth and a fifth super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in the first orientation of the first super junction structure, having an orientation almost perpendicular to the first super junction structure,   wherein the first to fifth super junction structures are formed by a trench epitaxial filling technique.   
     
     
         20 . A method for manufacturing a semiconductor device, the semiconductor device comprising:
 (a) a semiconductor chip region over a wafer having a first main surface with a source electrode of a power MOSFET thereover and a second main surface with a drain electrode of the power MOSFET thereover;   (b) a virtually rectangular cell region provided almost in the center of the first main surface, a peripheral side region provided along each side of the cell region, and a peripheral corner region provided in each corner of the cell region;   (c) a first-conductivity type drift region provided in virtually whole surfaces of the cell region, each peripheral side region, and each peripheral corner region over the first main surface of the semiconductor chip;   (d) a first super junction structure provided in the drift region over a virtually whole surface of the cell region, having a first orientation;   (e) a second and a third super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in the first orientation of the first super junction structure and coupled to the first super junction structure, having almost the same length and orientation as the first super junction structure; and   (f) a fourth and a fifth super junction structure provided in the drift region of the peripheral side regions on both sides of the cell region in a direction perpendicular to the first orientation of the first super junction structure, having an orientation almost perpendicular to the first super junction structure,   wherein the first to fifth super junction structures are formed by a trench epitaxial filling technique.